SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
For data integrity, the EMIF1 supports ECC on the data written or read from the SDRAM and is enabled by programming the EMIF_ECC_CTRL_REG register. ECC accesses are allowed for the both SYS and the MPU ports. 7-bit ECC is calculated over 32-bit data when in 32-bit DDR mode. 6-bit ECC is calculated over 16-bit data when in 16-bit DDR mode. The ECC is calculated for all accesses that are within the address ranges protected by ECC. The address ranges are specified in the EMIF_ECC_ADDRESS_RANGE_1 and EMIF_ECC_ADDRESS_RANGE_2 registers. Both registers have identical bits and functionality. This provides flexibility allowing two non-overlapping memory regions to be ECC protected.
The system must ensure that any burst access with starting address in the ECC protected region must not cross over to the un-protected region and vice-versa. The ECC is stored inside the SDRAM during writes. When RMW functionality is disabled, if a write access with byte count that is not a multiple of ECC quanta or with a non quanta aligned address is performed within the address range protected by ECC, the EMIF will send out a write ECC error interrupt. The EMIF will also report an error on the SYS and MPU response interface. In this case, the EMIF will perform the write to the SDRAM. However, the ECC value written to the SDRAM will be corrupted. The EMIF will also log the MConnID, MCmd, MBurstSeq, and MAddrSpace for the first error transaction in the EMIF_OCP_ERROR_LOG register and MAddr in the EMIF_OCP_ERR_ADDR_LOG register.
When RMW functionality is enabled, the EMIF provides a valid ECC for all data written regardless of alignment and byte count. The EMIF performs a RMW operation if a sub-quanta write is issued including for sub-quanta or quanta-misaligned 2D write accesses. For details on how RMW operations are performed, see Section 17.3.4.14.1, Read-Modify-Write Module.
The ECC quanta is either 32 bit or 16 bit based on the EMIF_SDRAM_CONFIG[15:14] NARROW_MODE bit field. For 32 bit mode (128 bits per EMIF clock cycle), an ECC quanta is 32 bits. For 16 bit narrow mode (64 bits per EMIF clock cycle), the ECC quanta is 16 bits.
Once ECC is enabled, the entire protected region must be initialized with data. These writes must be quanta-sized and quanta-aligned.
The ECC is read and verified during reads if EMIF_ECC_CTRL_REG[31] REG_ECC_EN = 0x1 and EMIF_ECC_CTRL_REG[29] REG_ECC_VERIFY_DIS = 0x0. For 1-bit ECC error in the data, the EMIF will correct the data and send it on the SYS or MPU return interface. The EMIF will log the starting address of the SDRAM burst in an internal 4 deep address FIFO. The internal FIFO will store the first four 1-bit ECC errors. The 1-Bit ECC Error Address Log register will display the address on top of the internal FIFO. The software must write a 0x1 to the EMIF_1B_ECC_ERR_ADDR_LOG register to pop the FIFO and display the next address stored. For subsequent reads in the ECC regions, the FIFO will be loaded with the address for the next 1-bit ECC error if it is not full. It must be noted that no address comparison will be performed, that is, if a single address has ECC errors back-to-back, that address will be logged twice.
The number of 1-bit ECC errors can be counted using the EMIF_1B_ECC_ERR_CNT register. The EMIF also supports programming a threshold and a window in the EMIF_1B_ECC_ERR_THRSH register. The window is programmed in number of refresh periods. When the programmed window value is 0x0, that is, window is disabled, and the internal error count meets the programmed threshold, the EMIF will generate a 1-bit ECC error interrupt. When servicing the interrupt the error count should be set with a value less than the threshold for triggering the interrupt again. When the programmed window value is non-zero, that is, window is enabled, the EMIF will generate a 1-bit ECC error interrupt only if the internal error count meets the programmed threshold in that window. The internal error count is reset every time the window expires. The software can use this to gauge the degree of 1-bit ECC errors occurring in the system.
For diagnosis, the EMIF supports a 1-Bit ECC data error distribution register (EMIF_1B_ECC_ERR_DIST_1 ) that represent whether an error has occurred in a given data channel location. This is advantageous to detect whether the errors are random or systemic. The distribution registers will be overlay of all 1-bit ECC errors until the software clears the register. Therefore, multiple bits could be set as a result of multiple 1-bit ECC errors occurring over multiple read accesses.
For 2-bit ECC errors in the data, the EMIF will generate a 2-bit ECC error interrupt. It must be noted that the EMIF will neither correct the data for these uncorrectable errors. Along with generating the interrupts, the EMIF will also report an error on the SYS or MPU return interface. In this case the EMIF will send the resultant data from the ECC correction logic. The read data received from the memory may have further been corrupted by the ECC correction logic since it will have attempted to correct the read data but failed due to uncorrectable error.
For all uncorrectable ECC errors listed above, the EMIF will log the starting address of the SDRAM burst in the EMIF_2B_ECC_ERR_ADDR_LOG register. This register will show the address of the first uncorrectable error. After the software clears the register, it will be loaded with the address for the next uncorrectable error.
In the event that the EMIF detects a single bit ECC error, although the error is corrected on the returned data, the data in the SDRAM is not corrected. It is the responsibility of the system software to correct the ECC error at that location. To the extent possible, the system software should correct multiple bit errors with the caveat that the returned data was not corrected but corrupted by the ECC correction logic.