SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
PD_DSP2 contains the following reset domains:
PD_DSP2 contains the CD_DSP2 clock domain.
Table 3-349 lists the logic retention capability for each module of the power domain.
Module | Logic Retention | DFF Context Status | RFF Context Status |
---|---|---|---|
DSP2 | No | RM_DSP2_DSP2_CONTEXT[1] LOSTCONTEXT_DFF | None |