SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
An interrupt enable bit in the MCSPI_IRQENABLE register can be set to enable each event to generate interrupt requests when the corresponding event occurs. Status bits are automatically set by hardware logic conditions.
When an event occurs (the single interrupt line is asserted), the MPU must :
The interrupt status bit must always be reset after channel enabling and before events are enabled as interrupt sources.