SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
CAL can perfom Tiler view memory access by configuring CTRL_CORE_SMA_SW_3[30] CAL_TILED_MEMORY_SPACE register bit. For more details, refer to L3_MAIN Memory Space Mapping, and Control Module.