SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The SIMCOP DMA module can generate two interrupts, SIMCOP_DMA_IRQ0 and SIMCOP_DMA_IRQ1. These two interrupts are controlled by four registers:
To clear an interrupt, software must write 1 in the corresponding bit of the SIMCOP_DMA_IRQSTATUS_j register even if the event is not enabled (SIMCOP_DMA_IRQSTATUS_RAW_j is also cleared).
Table 9-2640 list all the SIMCOP DMA events that can lead to an interrupt generation.
Bit Name | Bit | Event |
---|---|---|
BUS_ERR | 0 | Error occurred on bus |
CHAN0_BLOCK_DONE_IRQ | 16 | Channel 0 has completed transfer of one 2D block. |
CHAN1_BLOCK_DONE_IRQ | 17 | Channel 1 has completed transfer of one 2D block. |
CHAN2_BLOCK_DONE_IRQ | 18 | Channel 2 has completed transfer of one 2D block. |
CHAN3_BLOCK_DONE_IRQ | 19 | Channel 3 has completed transfer of one 2D block. |
CHAN4_BLOCK_DONE_IRQ | 20 | Channel 4 has completed transfer of one 2D block. |
CHAN5_BLOCK_DONE_IRQ | 21 | Channel 5 has completed transfer of one 2D block. |
CHAN6_BLOCK_DONE_IRQ | 22 | Channel 6 has completed transfer of one 2D block. |
CHAN7_BLOCK_DONE_IRQ | 23 | Channel 7 has completed transfer of one 2D block. |
CHAN0_FRAME_DONE_IRQ | 24 | Channel 0 has completed transfer of the full frame. |
CHAN1_FRAME_DONE_IRQ | 25 | Channel 1 has completed transfer of the full frame. |
CHAN2_FRAME_DONE_IRQ | 26 | Channel 2 has completed transfer of the full frame. |
CHAN3_FRAME_DONE_IRQ | 27 | Channel 3 has completed transfer of the full frame. |
CHAN4_FRAME_DONE_IRQ | 28 | Channel 4 has completed transfer of the full frame. |
CHAN5_FRAME_DONE_IRQ | 29 | Channel 5 has completed transfer of the full frame. |
CHAN6_FRAME_DONE_IRQ | 30 | Channel 6 has completed transfer of the full frame. |
CHAN7_FRAME_DONE_IRQ | 31 | Channel 7 has completed transfer of the full frame. |