SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Table 16-12 and Table 16-13 list the exported reset values and mapping, respectively.
MRM_PERMISSION_REGION_LOW_j [15:12] | MRM_PERMISSION_REGION_LOW_j [11:0] |
---|---|
0x0 | 0xFFF |
0xF | 0xFFF |
0x0 | 0xFFF |
0x2 | 0xFFF |
CONTROL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_1 and CONTROL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_1 Bits | Slave NIU Firewall |
---|---|
[0] | GPMC |
[3] | L3 RAM1 |
[4] | DSS |
[6] | GPU |
[7] | IVAHD SL2IF |
[8] | IVAHD CONFIG |
[11] | EMIF and MA_MPU_NTTP |
[12] | DEBUGSS |
[13] | CT_TBR |
[16] | EVE1 |
[17] | EVE2 |
[18] | ISS |
[20] | PCIESS1 |
[21] | PCIESS2 |
[22] | IPU1 |
[23] | IPU2 |
[24] | VCP1 |
[25] | VCP2 |
[26] | McASP1 |
[27] | McASP2 |
[28] | McASP3 |
[31] | BB2D |
CONTROL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_LOCK_2 and CONTROL_CORE_L3_HW_FW_EXPORTED_VALUES_CONF_DBG_2 Bits | Slave NIU Firewall |
---|---|
[0] | DSP1 |
[1] | DSP2 |
[2] | L3 RAM2 |
[3] | L3 RAM3 |
[8] | QSPI |
[9] | EDMA TC |
[10] | EDMA TPCC |
For more information, see Chapter 20, Control Module.