SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The MDIO clock is based on a divide-down of the interface (MAIN_CLK) clock, running at 125 MHz.The application software or driver must control the divide-down value.
See the MDIO_CONTROL register for configuring the Clock Divider (CLKDIV) value.