SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The ISP always uses the rising edge of the pixel clock to sample the pixel data. The ISP provides the capability to invert the pixel clock so it can shift the resampling of a pixel clock period by half. This is controlled by the ISP5_CTRL[22] PCLK_INV bit. By default, the inversion is disabled. The pixel clock must be disabled at ISS level before setting the PCLK_INV bit to 0x1. This can be done through the proper ISS_CLKCTRL[] <module>_PCLK register bit on ISS top level, depending on the interface that is sending data on the ISP video port.
The 4 bits in Table 9-172 are resynchronized from the GCK_MMR clock domain to the PCLK clock domain. There must be at least three clock cycles between the time these bits are modified and the HD/VD pulse for start of frame comes.
Module | Register | Bit Field |
---|---|---|
ISP | ISP5_CTRL | VD_PULSE_EXT |
ISIF | ISIF_MODESET | HDVDD |
ISIF | ISIF_MODESET | FIDD |
ISP | ISP5_CTRL | ISIF_CLK_ENABLE |