SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Register Name | Type | Register Width (Bits) | Address Offset | MAILBOX1 L4_CFG Physical Address |
---|---|---|---|---|
MAILBOX_REVISION | R | 32 | 0x0000 0000 | 0x4A0F 4000 |
MAILBOX_SYSCONFIG | RW | 32 | 0x0000 0010 | 0x4A0F 4010 |
MAILBOX_MESSAGE_m (1) | RW | 32 | 0x0000 0040 + (0x4 * m) | 0x4A0F 4040 + (0x4 * m) |
MAILBOX_FIFOSTATUS_m (1) | R | 32 | 0x0000 0080 + (0x4 * m) | 0x4A0F 4080 + (0x4 * m) |
MAILBOX_MSGSTATUS_m (1) | R | 32 | 0x0000 00C0 + (0x4 * m) | 0x4A0F 40C0 + (0x4 * m) |
MAILBOX_IRQSTATUS_RAW_u (2) | RW | 32 | 0x0000 0100 + (0x10 * u) | 0x4A0F 4100 + (0x10 * u) |
MAILBOX_IRQSTATUS_CLR_u (2) | RW | 32 | 0x0000 0104 + (0x10 * u) | 0x4A0F 4104 + (0x10 * u) |
MAILBOX_IRQENABLE_SET_u (2) | RW | 32 | 0x0000 0108 + (0x10 * u) | 0x4A0F 4108 + (0x10 * u) |
MAILBOX_IRQENABLE_CLR_u (2) | RW | 32 | 0x0000 010C + (0x10 * u) | 0x4A0F 410C + (0x10 * u) |
MAILBOX_IRQ_EOI | W | 32 | 0x0000 0140 | 0x4A0F 4140 |
Register Name | Type | Register Width (Bits) | Address Offset | MAILBOX2 L4_PER3 Physical Address | MAILBOX3 L4_PER3 Physical Address | MAILBOX4 L4_PER3 Physical Address |
---|---|---|---|---|---|---|
MAILBOX_REVISION | R | 32 | 0x0000 0000 | 0x4883 A000 | 0x4883 C000 | 0x4883 E000 |
MAILBOX_SYSCONFIG | RW | 32 | 0x0000 0010 | 0x4883 A010 | 0x4883 C010 | 0x4883 E010 |
MAILBOX_MESSAGE_m (1) | RW | 32 | 0x0000 0040 + (0x4 * m) | 0x4883 A040 + (0x4 * m) | 0x4883 C040 + (0x4 * m) | 0x4883 E040 + (0x4 * m) |
MAILBOX_FIFOSTATUS_m (1) | R | 32 | 0x0000 0080 + (0x4 * m) | 0x4883 A080 + (0x4 * m) | 0x4883 C080 + (0x4 * m) | 0x4883 E080 + (0x4 * m) |
MAILBOX_MSGSTATUS_m (1) | R | 32 | 0x0000 00C0 + (0x4 * m) | 0x4883 A0C0 + (0x4 * m) | 0x4883 C0C0 + (0x4 * m) | 0x4883 E0C0 + (0x4 * m) |
MAILBOX_IRQSTATUS_RAW_u (2) | RW | 32 | 0x0000 0100 + (0x10 * u) | 0x4883 A100 + (0x10 * u) | 0x4883 C100 + (0x10 * u) | 0x4883 E100 + (0x10 * u) |
MAILBOX_IRQSTATUS_CLR_u (2) | RW | 32 | 0x0000 0104 + (0x10 * u) | 0x4883 A104 + (0x10 * u) | 0x4883 C104 + (0x10 * u) | 0x4883 E104 + (0x10 * u) |
MAILBOX_IRQENABLE_SET_u (2) | RW | 32 | 0x0000 0108 + (0x10 * u) | 0x4883 A108 + (0x10 * u) | 0x4883 C108 + (0x10 * u) | 0x4883 E108 + (0x10 * u) |
MAILBOX_IRQENABLE_CLR_u (2) | RW | 32 | 0x0000 010C + (0x10 * u) | 0x4883 A10C + (0x10 * u) | 0x4883 C10C + (0x10 * u) | 0x4883 E10C + (0x10 * u) |
MAILBOX_IRQ_EOI | W | 32 | 0x0000 0140 | 0x4883 A140 | 0x4883 C140 | 0x4883 E140 |
Register Name | Type | Register Width (Bits) | Address Offset | MAILBOX5 L4_PER3 Physical Address | MAILBOX6 L4_PER3 Physical Address | MAILBOX7 L4_PER3 Physical Address |
---|---|---|---|---|---|---|
MAILBOX_REVISION | R | 32 | 0x0000 0000 | 0x4884 0000 | 0x4884 2000 | 0x4884 4000 |
MAILBOX_SYSCONFIG | RW | 32 | 0x0000 0010 | 0x4884 0010 | 0x4884 2010 | 0x4884 4010 |
MAILBOX_MESSAGE_m (1) | RW | 32 | 0x0000 0040 + (0x4 * m) | 0x4884 0040 + (0x4 * m) | 0x4884 2040 + (0x4 * m) | 0x4884 4040 + (0x4 * m) |
MAILBOX_FIFOSTATUS_m (1) | R | 32 | 0x0000 0080 + (0x4 * m) | 0x4884 0080 + (0x4 * m) | 0x4884 2080 + (0x4 * m) | 0x4884 4080 + (0x4 * m) |
MAILBOX_MSGSTATUS_m (1) | R | 32 | 0x0000 00C0 + (0x4 * m) | 0x4884 00C0 + (0x4 * m) | 0x4884 20C0 + (0x4 * m) | 0x4884 40C0 + (0x4 * m) |
MAILBOX_IRQSTATUS_RAW_u (2) | RW | 32 | 0x0000 0100 + (0x10 * u) | 0x4884 0100 + (0x10 * u) | 0x4884 2100 + (0x10 * u) | 0x4884 4100 + (0x10 * u) |
MAILBOX_IRQSTATUS_CLR_u (2) | RW | 32 | 0x0000 0104 + (0x10 * u) | 0x4884 0104 + (0x10 * u) | 0x4884 2104 + (0x10 * u) | 0x4884 4104 + (0x10 * u) |
MAILBOX_IRQENABLE_SET_u (2) | RW | 32 | 0x0000 0108 + (0x10 * u) | 0x4884 0108 + (0x10 * u) | 0x4884 2108 + (0x10 * u) | 0x4884 4108 + (0x10 * u) |
MAILBOX_IRQENABLE_CLR_u (2) | RW | 32 | 0x0000 010C + (0x10 * u) | 0x4884 010C + (0x10 * u) | 0x4884 210C + (0x10 * u) | 0x4884 410C + (0x10 * u) |
MAILBOX_IRQ_EOI | W | 32 | 0x0000 0140 | 0x4884 0140 | 0x4884 2140 | 0x4884 4140 |
Register Name | Type | Register Width (Bits) | Address Offset | MAILBOX8 L4_PER3 Physical Address | MAILBOX9 L4_PER3 Physical Address | MAILBOX10 L4_PER3 Physical Address |
---|---|---|---|---|---|---|
MAILBOX_REVISION | R | 32 | 0x0000 0000 | 0x4884 6000 | 0x4885 E000 | 0x4886 0000 |
MAILBOX_SYSCONFIG | RW | 32 | 0x0000 0010 | 0x4884 6010 | 0x4885 E010 | 0x4886 0010 |
MAILBOX_MESSAGE_m (1) | RW | 32 | 0x0000 0040 + (0x4 * m) | 0x4884 6040 + (0x4 * m) | 0x4885 E040 + (0x4 * m) | 0x4886 0040 + (0x4 * m) |
MAILBOX_FIFOSTATUS_m (1) | R | 32 | 0x0000 0080 + (0x4 * m) | 0x4884 6080 + (0x4 * m) | 0x4885 E080 + (0x4 * m) | 0x4886 0080 + (0x4 * m) |
MAILBOX_MSGSTATUS_m (1) | R | 32 | 0x0000 00C0 + (0x4 * m) | 0x4884 60C0 + (0x4 * m) | 0x4885 E0C0 + (0x4 * m) | 0x4886 00C0 + (0x4 * m) |
MAILBOX_IRQSTATUS_RAW_u (2) | RW | 32 | 0x0000 0100 + (0x10 * u) | 0x4884 6100 + (0x10 * u) | 0x4885 E100 + (0x10 * u) | 0x4886 0100 + (0x10 * u) |
MAILBOX_IRQSTATUS_CLR_u (2) | RW | 32 | 0x0000 0104 + (0x10 * u) | 0x4884 6104 + (0x10 * u) | 0x4885 E104 + (0x10 * u) | 0x4886 0104 + (0x10 * u) |
MAILBOX_IRQENABLE_SET_u (2) | RW | 32 | 0x0000 0108 + (0x10 * u) | 0x4884 6108 + (0x10 * u) | 0x4885 E108 + (0x10 * u) | 0x4886 0108 + (0x10 * u) |
MAILBOX_IRQENABLE_CLR_u (2) | RW | 32 | 0x0000 010C + (0x10 * u) | 0x4884 610C + (0x10 * u) | 0x4885 E10C + (0x10 * u) | 0x4886 010C + (0x10 * u) |
MAILBOX_IRQ_EOI | W | 32 | 0x0000 0140 | 0x4884 6140 | 0x4885 E140 | 0x4886 0140 |
Register Name | Type | Register Width (Bits) | Address Offset | MAILBOX11 L4_PER3 Physical Address | MAILBOX12 L4_PER3 Physical Address | MAILBOX13 L4_PER3 Physical Address |
---|---|---|---|---|---|---|
MAILBOX_REVISION | R | 32 | 0x0000 0000 | 0x4886 2000 | 0x4886 4000 | 0x4880 2000 |
MAILBOX_SYSCONFIG | RW | 32 | 0x0000 0010 | 0x4886 2010 | 0x4886 4010 | 0x4880 2010 |
MAILBOX_MESSAGE_m (1) | RW | 32 | 0x0000 0040 + (0x4 * m) | 0x4886 2040 + (0x4 * m) | 0x4886 4040 + (0x4 * m) | 0x4880 2040 + (0x4 * m) |
MAILBOX_FIFOSTATUS_m (1) | R | 32 | 0x0000 0080 + (0x4 * m) | 0x4886 2080 + (0x4 * m) | 0x4886 4080 + (0x4 * m) | 0x4880 2080 + (0x4 * m) |
MAILBOX_MSGSTATUS_m (1) | R | 32 | 0x0000 00C0 + (0x4 * m) | 0x4886 20C0 + (0x4 * m) | 0x4886 40C0 + (0x4 * m) | 0x4880 20C0 + (0x4 * m) |
MAILBOX_IRQSTATUS_RAW_u (2) | RW | 32 | 0x0000 0100 + (0x10 * u) | 0x4886 2100 + (0x10 * u) | 0x4886 4100 + (0x10 * u) | 0x4880 2100 + (0x10 * u) |
MAILBOX_IRQSTATUS_CLR_u (2) | RW | 32 | 0x0000 0104 + (0x10 * u) | 0x4886 2104 + (0x10 * u) | 0x4886 4104 + (0x10 * u) | 0x4880 2104 + (0x10 * u) |
MAILBOX_IRQENABLE_SET_u (2) | RW | 32 | 0x0000 0108 + (0x10 * u) | 0x4886 2108 + (0x10 * u) | 0x4886 4108 + (0x10 * u) | 0x4880 2108 + (0x10 * u) |
MAILBOX_IRQENABLE_CLR_u (2) | RW | 32 | 0x0000 010C + (0x10 * u) | 0x4886 210C + (0x10 * u) | 0x4886 410C + (0x10 * u) | 0x4880 210C + (0x10 * u) |
MAILBOX_IRQ_EOI | W | 32 | 0x0000 0140 | 0x4886 2140 | 0x4886 4140 | 0x4880 2140 |
Register Name | Type | Register Width (Bits) | Address Offset | IVA_MBOX L3_MAIN Physical Address |
---|---|---|---|---|
MAILBOX_REVISION | R | 32 | 0x0000 0000 | 0x5A05 A800 |
MAILBOX_SYSCONFIG | RW | 32 | 0x0000 0010 | 0x5A05 A810 |
MAILBOX_MESSAGE_m (1) | RW | 32 | 0x0000 0040 + (0x4 * m) | 0x5A05 A840 + (0x4 * m) |
MAILBOX_FIFOSTATUS_m (1) | R | 32 | 0x0000 0080 + (0x4 * m) | 0x5A05 A880 + (0x4 * m) |
MAILBOX_MSGSTATUS_m (1) | R | 32 | 0x0000 00C0 + (0x4 * m) | 0x5A05 A8C0 + (0x4 * m) |
MAILBOX_IRQSTATUS_RAW_u (2) | RW | 32 | 0x0000 0100 + (0x10 * u) | 0x5A05 A900 + (0x10 * u) |
MAILBOX_IRQSTATUS_CLR_u (2) | RW | 32 | 0x0000 0104 + (0x10 * u) | 0x5A05 A904 + (0x10 * u) |
MAILBOX_IRQENABLE_SET_u (2) | RW | 32 | 0x0000 0108 + (0x10 * u) | 0x5A05 A908 + (0x10 * u) |
MAILBOX_IRQENABLE_CLR_u (2) | RW | 32 | 0x0000 010C + (0x10 * u) | 0x5A05 A90C + (0x10 * u) |
MAILBOX_IRQ_EOI | W | 32 | 0x0000 0140 | 0x5A05 A940 |
Register Name | Type | Register Width (Bits) | Address Offset | EVE1_MBOX0 L3_MAIN Physical Address | EVE1_MBOX1 L3_MAIN Physical Address | EVE1_MBOX2 L3_MAIN Physical Address |
---|---|---|---|---|---|---|
MAILBOX_REVISION | R | 32 | 0x0000 0000 | 0x4208 B000 | 0x4208 C000 | 0x4208 D000 |
MAILBOX_SYSCONFIG | RW | 32 | 0x0000 0010 | 0x4208 B010 | 0x4208 C010 | 0x4208 D010 |
MAILBOX_MESSAGE_m (1) | RW | 32 | 0x0000 0040 + (0x4 * m) | 0x4208 B040 + (0x4 * m) | 0x4208 C040 + (0x4 * m) | 0x4208 D040 + (0x4 * m) |
MAILBOX_FIFOSTATUS_m (1) | R | 32 | 0x0000 0080 + (0x4 * m) | 0x4208 B080 + (0x4 * m) | 0x4208 C080 + (0x4 * m) | 0x4208 D080 + (0x4 * m) |
MAILBOX_MSGSTATUS_m (1) | R | 32 | 0x0000 00C0 + (0x4 * m) | 0x4208 B0C0 + (0x4 * m) | 0x4208 C0C0 + (0x4 * m) | 0x4208 D0C0 + (0x4 * m) |
MAILBOX_IRQSTATUS_RAW_u (2) | RW | 32 | 0x0000 0100 + (0x10 * u) | 0x4208 B100 + (0x10 * u) | 0x4208 C100 + (0x10 * u) | 0x4208 D100 + (0x10 * u) |
MAILBOX_IRQSTATUS_CLR_u (2) | RW | 32 | 0x0000 0104 + (0x10 * u) | 0x4208 B104 + (0x10 * u) | 0x4208 C104 + (0x10 * u) | 0x4208 D104 + (0x10 * u) |
MAILBOX_IRQENABLE_SET_u (2) | RW | 32 | 0x0000 0108 + (0x10 * u) | 0x4208 B108 + (0x10 * u) | 0x4208 C108 + (0x10 * u) | 0x4208 D108 + (0x10 * u) |
MAILBOX_IRQENABLE_CLR_u (2) | RW | 32 | 0x0000 010C + (0x10 * u) | 0x4208 B10C + (0x10 * u) | 0x4208 C10C + (0x10 * u) | 0x4208 D10C + (0x10 * u) |
MAILBOX_IRQ_EOI | W | 32 | 0x0000 0140 | 0x4208 B140 | 0x4208 C140 | 0x4208 D140 |
Register Name | Type | Register Width (Bits) | Address Offset | EVE2_MBOX0 L3_MAIN Physical Address | EVE2_MBOX1 L3_MAIN Physical Address | EVE2_MBOX2 L3_MAIN Physical Address |
---|---|---|---|---|---|---|
MAILBOX_REVISION | R | 32 | 0x0000 0000 | 0x4218 B000 | 0x4218 C000 | 0x4218 D000 |
MAILBOX_SYSCONFIG | RW | 32 | 0x0000 0010 | 0x4218 B010 | 0x4218 C010 | 0x4218 D010 |
MAILBOX_MESSAGE_m (1) | RW | 32 | 0x0000 0040 + (0x4 * m) | 0x4218 B040 + (0x4 * m) | 0x4218 C040 + (0x4 * m) | 0x4218 D040 + (0x4 * m) |
MAILBOX_FIFOSTATUS_m (1) | R | 32 | 0x0000 0080 + (0x4 * m) | 0x4218 B080 + (0x4 * m) | 0x4218 C080 + (0x4 * m) | 0x4218 D080 + (0x4 * m) |
MAILBOX_MSGSTATUS_m (1) | R | 32 | 0x0000 00C0 + (0x4 * m) | 0x4218 B0C0 + (0x4 * m) | 0x4218 C0C0 + (0x4 * m) | 0x4218 D0C0 + (0x4 * m) |
MAILBOX_IRQSTATUS_RAW_u (2) | RW | 32 | 0x0000 0100 + (0x10 * u) | 0x4218 B100 + (0x10 * u) | 0x4218 C100 + (0x10 * u) | 0x4218 D100 + (0x10 * u) |
MAILBOX_IRQSTATUS_CLR_u (2) | RW | 32 | 0x0000 0104 + (0x10 * u) | 0x4218 B104 + (0x10 * u) | 0x4218 C104 + (0x10 * u) | 0x4218 D104 + (0x10 * u) |
MAILBOX_IRQENABLE_SET_u (2) | RW | 32 | 0x0000 0108 + (0x10 * u) | 0x4218 B108 + (0x10 * u) | 0x4218 C108 + (0x10 * u) | 0x4218 D108 + (0x10 * u) |
MAILBOX_IRQENABLE_CLR_u (2) | RW | 32 | 0x0000 010C + (0x10 * u) | 0x4218 B10C + (0x10 * u) | 0x4218 C10C + (0x10 * u) | 0x4218 D10C + (0x10 * u) |
MAILBOX_IRQ_EOI | W | 32 | 0x0000 0140 | 0x4218 B140 | 0x4218 C140 | 0x4218 D140 |