SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The McSPI detects the end of the wake period through the idle and wake-up hardware handshake protocol.
The interrupt status register (the MCSPI_IRQSTATUS[16] WKS bit) is updated with the event causing the wakeup; the wake-up event at the origin of the transition to the normal mode is converted to its corresponding interrupt when enabled by the MCSPI_IRQENABLE[16] WKE bit or the DMA request.
Interrupts and wake-up events have independent enable and disable controls, accessible through the MCSPI_IRQENABLE and MCSPI_WAKEUPENABLE registers. Software must ensure the overall consistency.
The interrupt status register MCSPI_IRQSTATUS is updated with the event causing the wakeup; the wake-up event at the origin of the transition to normal mode is converted to its corresponding interrupt request or DMA request. The module is fully operational.