SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
This section contains high-level examples of the programming sequences for common SCTM user scenarios. The following examples assume that the counter timer module is already enabled by setting the ENBL bit in the SCTM_CTCNTL register to 1. The examples also assume that the CTCRn:ENBL bit is cleared before any configuration writes other than RESET.