SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
Software must fully configure a DMA channel before enabling it. It then configures channel linking and the used synchronization method.
The following example shows four logical channels chained with hardware synchronization used to copy YUV4:2:0-NV12 data from SIMCOP local memories to system memory, and then to copy YUV4:2:0-NV12 data from system memory to SIMCOP local memories.
YUV4:2:0-NV12 data is stored in two separate buffers in SDRAM. Therefore, two channels are used for the SIMCOP -> system copy, and two channels are used for the system -> SIMCOP copy.
In this example, the intent is to transfer a 2 x 2 array of 64 x 32 pixel blocks. It is assumed that input data is stored contiguously in system memory and that the output buffer size in system memory is 256 x 32 pixels. In SIMCOP local memories, data is contiguously stored starting at address 0
The following configuration is used:
Figure 9-192 shows the channel linking chain used. All four channels are executed sequentially. Doing so prevents access collision in SIMCOP local memories or system memories. Channel 0 is started by a START[0] pulse from SIMCOP. When Channel 3 completes the last transfer, a pulse to DONE[0] is sent back to SIMCOP.
Figure 9-193 shows the temporal channel sequence.
The following configuration is used for each channel:
Software can read the status of a logical channel at any time. However, logical channel configuration registers can be changed only when the channel is in the IDLE state.
Software can disable a logical channel by writing the SIMCOP_DMA_CHAN_CTRL_i[1] DISABLE bit. A channel is effectively disabled when SIMCOP_DMA_CHAN_CTRL_i[4:3] STATUS = IDLE. In case of linked channels, software must disable all channels in the chain and wait until all of them are back in the IDLE state before channels can be reprogrammed.