SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
As a target of the device L3_MAIN bus (with target being the PCIe controller slave port on L3_MAIN respectively), the controller supports the "Idle" protocol. The behaviour of that interface can be configured in the PCIeSS controller wrapper register - PCIECTRL_TI_CONF_SYSCONFIG[3:2] IDLEMODE bitfield.
Additionally, the slave port clock management supports a disconnect protocol which is controlled automatically.
The idle transition of the PCIe controller is strictly synchronized to PIPE clock. The PRCM places the PCIe controller to an "Idle state" before PCIePCS generated PIPE clock is stopped due to some reason: g.h. PCIe PHY low power transition with gating local PLL clocks, the APLL_PCIe clock or gating PCIeREF_DPLL clock. The IDLE state is automatically maintained by PRCM during periods in which PIPE clock is stopped.
PCIe controller transitions to IDLE initiated by the system PRCM are strictly synchronized with the PCIe operational state. The PRCM allows the PCIe controller to be brought out of "IDLE" state, only if the generation of the PIPE clock is enabled by configuring the high-frequency PLL (source of the PIPE clock) and the 100 MHz PCIe reference clock scheme (source of the high-frequency clock). For more details on the PCIe PLL and PHY related clocks, refer to the Section 28.4, PCIe Shared PHY Susbsystem in the chapter, Shared PHY Component Subsystems .
All accesses to the device PCIe controller on its slave port, namely to the local target configuration PL/PCIe standard/wrapper registers or to the PCIe bus, require the PIPE clock to be running. The presence of the PCIe interface clock - PCIE_L3_GICLK is not sufficient to perform such accesses.