SPRUIE9D May 2017 – May 2024 DRA74P , DRA75P , DRA76P , DRA77P
The PIPE_PCLK clock which drives the PIPE3 logic is sourced by the on-chip USB3_PHY. The PIPE interface is source-synchronous (that is, the clock is received from the PHY), used to synchronize USB1 PIPE inputs, and reflected back along with the PIPE outputs as the PIPE_MCLK. The PIPE_PCLK clock is turned on/off according to the USB3_PHY power control port. For more details, see Section 28.2.4.2.3, USB3_PHY Power Management.