This section explains the fundamental
process of reception in the McBSP. For details about how to program the McBSP
receiver, see Section 34.8.
Figure 34-13 and Figure 34-14 show how reception occurs in the McBSP. Figure 34-13 shows the physical path for the data. Figure 34-14 is a timing diagram showing signal activity for one possible reception scenario.
A description of the process follows the figures.
The following process describes how
data travels from the DR pin to the CPU or to the DMA controller:
- The McBSP waits for a receive
frame-synchronization pulse on internal FSR.
- When the pulse arrives, the McBSP
inserts the appropriate data delay that is selected with the RDATDLY bits of
RCR2.
In the preceding timing diagram, a 1-bit
data delay is selected.
- The McBSP accepts data bits on
the DR pin and shifts them into the receive shift registers.
If the word length is 16 bits or smaller, only
RSR1 is used. If the word length is larger than 16 bits, RSR2 and RSR1 are used
and RSR2 contains the most-significant bits. For details on choosing a word
length, see Section 34.8.8.
- When a full word is received, the
McBSP copies the contents of the receive shift registers to the receive buffer
registers, provided that RBR1 is not full with previous data.
If the word length is 16 bits or smaller, only
RBR1 is used. If the word length is larger than 16 bits, RBR2 and RBR1 are used
and RBR2 contains the most-significant bits.
- The McBSP copies the contents of
the receive buffer registers into the data receive registers, provided that DRR1
is not full with previous data. When DRR1 receives new data, the receiver ready
bit (RRDY) is set in SPCR1. This indicates that received data is ready to be
read by the CPU or the DMA controller.
If the word
length is 16 bits or smaller, only DRR1 is used. If the word length is larger
than 16 bits, DRR2 and DRR1 are used and DRR2 contains the most-significant
bits.
If companding is used during the copy
(RCOMPAND = 10b or 11b in RCR2), the 8-bit compressed data in RBR1 is expanded
to a left-justified 16-bit value in DRR1. If companding is disabled, the data
copied from RBR[1,2] to DRR[1,2] is justified and bit filled according to the
RJUST bits.
- The CPU or the DMA controller
reads the data from the data receive registers. When DRR1 is read, RRDY is
cleared and the next RBR-to-DRR copy is initiated.
Note: If both DRRs are required (word
length larger than 16 bits), the CPU or the DMA controller must read from DRR2 first
and then from DRR1. As soon as DRR1 is read, the next RBR-to-DRR copy is initiated.
If DRR2 is not read first, the data in DRR2 is lost.
When activity is not properly timed,
errors can occur. See the following topics for more details: