Operation and features of the eCAP
interrupt control include (see Figure 24-9):
- An interrupt can be generated on capture events (CEVT1-CEVT4,
CTROVF) or APWM events (CTR = PRD, CTR = CMP).
- A counter overflow event (FFFFFFFF->00000000) is also
provided as an interrupt source (CTROVF).
- The capture events are edge and sequencer-qualified (ordered in
time) by the polarity select and Mod4 gating, respectively.
- One of these events can be selected as the interrupt source
(from the eCAPx module) going to the PIE and CLA.
- Seven interrupt events (CEVT1, CEVT2, CEVT3, CEVT4, CNTOVF,
CTR=PRD, CTR=CMP) can be generated.
- The interrupt enable register
(ECEINT) is used to enable/disable individual interrupt event sources. The
interrupt flag register (ECFLG) indicates if any interrupt event has been
latched and contains the global interrupt flag bit (INT). An interrupt pulse is
generated to the PIE only if any of
the interrupt events are enabled, the flag bit is 1, and the INT flag bit is 0.
The interrupt service routine must clear the global interrupt flag bit and the
serviced event using the interrupt clear register (ECCLR) before any other
interrupt pulses are generated. All interrupt flags are cleared upon an event filter reset by writing a 1
to ECCTL2[CLRFILTRESET]. To force an interrupt event, use the interrupt
force register (ECFRC). This is useful for test purposes.
Note: The CEVT1, CEVT2, CEVT3, CEVT4
flags are only active in capture mode (ECCTL2[CAP/APWM == 0]). The CTR=PRD, CTR=CMP
flags are only valid in APWM mode (ECCTL2[CAP/APWM == 1]). CNTOVF flag is valid in
both modes.