The I2C modules support the following features:
- Devices on the I2C bus can be designated as
either a master or a slave.
- Supports both
transmitting and receiving data as either a master or a
slave
- Supports simultaneous master and slave
operation
- Four I2C modes:
- Master transmit
- Master receive
- Slave transmit
- Slave receive
- Receive FIFO and Transmitter FIFO (8 deep x 8 bits FIFO)
- FIFOs can be independently assigned to master or slave
- Four transmission speeds:
- Standard (100 kbps)
- Fast mode (400 kbps)
- Fast-mode plus (1 Mbps)
- High-speed mode (3.33 Mbps)
- Glitch suppression
- SMBus support through software
- Clock low time-out interrupt
- Dual slave address
capability
- Quick command capability
- Master and slave
interrupt generation
- Master
generates interrupts when a transmit or receive operation completes (or
aborts because of an error)
- Slave
generates interrupts when data has been transferred or requested by a
master or when
a START or STOP condition is detected
- Master with arbitration and clock synchronization, multiple-master support, and
7-bit addressing mode
- Efficient transfers using a Micro Direct Memory Access Controller (µDMA)
- Separate channels for transmit and receive
- Ability to execute single data transfers or burst data transfers using the RX and TX FIFOs in the I2C