SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 43-62 describes the read format of the RDES3 Normal Descriptor.
31 | 30 | 19-26 | 25 | 24 | 23:0 |
---|---|---|---|---|---|
OWN | IOC | Rsvd | BUF2V | BUF1V | Rsvd |
Bit | Name | Description |
---|---|---|
31 | OWN | Own Bit |
When this bit is set, the bit indicates that the Ethernet module DMA owns the descriptor. When this bit is reset, the bit indicates that the application owns the descriptor. The DMA clears this bit when either of the following conditions is true: | ||
The DMA completes the packet reception | ||
The buffers associated with the descriptor are full | ||
30 | IOC | Interrupt Enabled on Completion |
When this bit is set, an interrupt is issued to the application when the DMA closes this descriptor. | ||
29-26 | Rsvd | Reserved |
25 | BUF2V | Buffer 2 Address Valid |
When this bit is set, the bit indicates to the DMA that the buffer 2 address specified in RDES2 is valid. The application must set this bit so that the DMA can use the address, to which the Buffer 2 address in RDES2 is pointing, to write received packet data. | ||
24 | BUF1V | Buffer 1 Address Valid |
When set, this indicates to the DMA that the buffer 1 address specified in RDES1 is valid. | ||
The application must set this value if the address pointed to by Buffer 1 address in RDES1 can be used by the DMA to write received packet data. | ||
23-0 | Rsvd | Reserved |