SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
The CM clock is derived from PLLSYSCLK or AUXPLLRAWCLK and then divided down by the CMCLK divider. This clock is asynchronous to the CPU1/CPU2 system clock. This clock is used by the Cortex®-M4 CPU (CM), GPIO, DCSM, Message RAMs, IPC and Watch Dog.