SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
To use the USB controller, the peripheral clock must be enabled using the System Control module PCLKCR11 register. In addition, the USB PHY signals must be connected to the respective pins using the GPIO module GPBAMSEL register. Set bits 10 and 11 for USB0DM (GPIO42) and USB0DP (GPIO43).
Set up the auxiliary PLL so a 60MHz output clock is provided to the USB module. This fixed frequency is required for all USB operations. See the System Control and Interrupts chapter for more details.
In host mode, the USB controller is responsible for supplying power to the bus. To avoid incorrectly supplying voltage to the bus, the external power control signal, USB0EPEN, must be kept inactive on start-up. This can be done by connecting the USB0EPEN and USB0PFLT pins to the USB controller as soon as possible.