SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
A main oscillator verification circuit is provided that generates an error condition if the oscillator is running too fast or too slow or goes missing. This logic is referred to as Missing Clock Detection. When a missing clock error is generated, the CLOCKFAIL bit (bit 1) of the CMNMIFLG register is set, the clock source is switched to the 10 MHz internal oscillator, and the PLL is bypassed.
The CLOCKFAIL NMI is triggered to both the CM and C28 subsystems. Since this NMI source is enabled by default on power up, it makes it necessary for boot ROM to handle this NMI. Refer to the Boot ROM chapter of this document for more details on how boot ROM handles this NMI.