SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
In this example, the frequency of CAN_CLK is 10MHz, BRP is 0, the bit rate is 1MBit/s.
tq | 100ns | = | tCAN_CLK |
delay of bus driver | 90ns | = | |
delay of receiver circuit | 40ns | = | |
delay of bus line (40m) | 220ns | = | |
tProp | 700ns | = | 2*delays = 7 • tq |
tSJW | 100ns | = | 1 • tq |
tTSeg1 | 800ns | = | tProp + tSJW |
tTSeg2 | 100ns | = | Information Processing Time + 1 • tq |
tSync-Seg | 100ns | = | 1 • tq |
bit time | 1000ns | = | tSync-Seg + tTSeg1 + tTSeg2 |
tolerance for CAN_CLK | 0.35% | = |
In this example, the concatenated bit time parameters are (1-1)3&(8-1)4&(1-1)2&(1-1)6, so the Bit Timing Register is programmed to = 0x0000 0700.