SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
For RMII mode operation, the module needs a 50MHz clock. The clock can be sourced internally (from the module) or can be sourced externally (from any external component through the RMII_CLK pin input). The CLK_SRC_SEL field of EMACSS_CTRLSTS register programs the source of the RMII clock, as shown in Figure 43-5.
If the external clock is selected, the ENET_RMII_CLK pin of the device must be provided with the required 50MHz clock.
If the internal mode is selected, the 50MHz clock generated internally must be used to clock the RMII module. Make sure that the clock source and divider are set accordingly to provide a 50MHz clock.