The following steps explain the FIFO features and help with programming the SPI FIFOs:
- Reset. At reset the SPI powers up in standard SPI mode and the FIFO function is disabled. The FIFO registers SPIFFTX, SPIFFRX and SPIFFCT remain inactive.
- Standard SPI. The standard 28x SPI mode
works with SPIINT/SPIRXINT as the interrupt source.
- Mode change. FIFO mode is enabled by
setting the SPIFFENA bit to 1 in the SPIFFTX register. SPIRST can reset the
FIFO mode at any stage of the operation.
- Active registers. All the SPI registers
and SPI FIFO registers SPIFFTX, SPIFFRX, and SPIFFCT are active.
- Interrupts. FIFO mode has two interrupts:
one for the transmit FIFO, SPITXINT; one for the receive FIFO, SPIRXINT.
SPIRXINT is the common interrupt for SPI FIFO receive, receive error and
receive FIFO overflow conditions. The single SPIINT for both transmit and
receive sections of the standard SPI are disabled and this interrupt is
serviced as SPI receive FIFO interrupt. For more information, refer to Section 37.2.3.
- Buffers. Transmit and receive buffers are
each supplemented with a 16-word FIFO. The one-word transmit buffer (SPITXBUF) of the
standard SPI functions as a transition buffer between the transmit FIFO and
shift register. The one-word transmit buffer is loaded from transmit FIFO
only after the last bit of the shift register is shifted out.
- Delayed transfer. The rate at which
transmit words in the FIFO are transferred to transmit shift register is
programmable. The SPIFFCT register bits (7−0) FFTXDLY7−FFTXDLY0 define the
delay between the word transfer. The delay is defined in number SPI serial
clock cycles. The 8-bit register can define a minimum delay of 0 SPICLK
cycles and a maximum of 255 SPICLK cycles. With zero delay, the SPI module
can transmit data in continuous mode with the FIFO words shifting out back
to back. With the 255 clock delay, the SPI module can transmit data in a
maximum delayed mode with the FIFO words shifting out with a delay of 255
SPICLK cycles between each words. The programmable delay facilitates
glueless interface to various slow SPI peripherals, such as EEPROMs, ADC,
DAC, and so on.
- FIFO status bits. Both transmit and
receive FIFOs have status bits TXFFST or RXFFST that define the number of
words available in the FIFOs at any time. The transmit FIFO reset bit
(TXFIFO) and receive reset bit (RXFIFO) reset the FIFO pointers to zero when
these bits are set to 1. The FIFOs resume operation from start once these
bits are cleared to zero.
- Programmable interrupt levels. Both
transmit and receive FIFOs can generate CPU interrupts and DMA triggers. The transmit interrupt (SPITXINT) is generated
whenever the transmit FIFO status bits (TXFFST) match (less than or equal
to) the interrupt trigger level bits (TXFFIL). The receive interrupt
(SPIRXINT) is generated whenever the receive FIFO status bits (RXFFST) match
(greater than or equal to) the interrupt trigger level RXFFIL. This provides
a programmable interrupt trigger for transmit and receive sections of the
SPI. The default value for these trigger level bits is 0x11111 for receive
FIFO and 0x00000 for transmit FIFO, respectively.