SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
CPU2 boot ROM health and booting status is written to a 32-bit address in M0RAM. This status is cleared on every CPU2 reset. Additionally, a copy of the status is written to CPU2TOCPU1IPCBOOTSTS for CPU1 to have access to CPU2's boot status.
Description | Address |
---|---|
CPU2 Boot ROM Status | 0x0000 0002 |
Bit | Description |
---|---|
31 | CPU2 Boot ROM has finished running |
30 | Missing clock NMI occurred |
29 | RAM Uncorrectable Error NMI or ROM Parity Error occurred |
28 | Flash Uncorrectable Error NMI occurred |
27 | HWBIST NMI occurred |
26 | PIE Vector NMI occurred |
25 | RL NMI occurred |
24 | PIE Mismatch occurred |
23 | ITRAP occurred |
22 | ERAD NMI occurred |
21 | Secure Flash Boot CMAC returned failure |
20 | Not Used |
19 | Invalid length specified in CPU1TOCPU2IPCBOOTMODE for IPC message RAM copy length |
18 | Invalid (or missing configuration) in CPU1TOCPU2IPCBOOTMODE |
17 | RAM Initialization Complete |
16 | Not Used |
15 | HWBIST Reset Handled |
14 | POR Reset Handled |
13 | XRS Reset Handled |
12 | All Resets Handled |
11:8 | Not Used |
7:0 | 0x0 = Invalid / No Status set yet |
0x1 = CPU2 Boot ROM has started running | |
0x2 = Running Flash Boot | |
0x3 = Running Secure Flash Boot | |
0x4 = Running IPC Message Copy to RAM Boot | |
0x5 = Running RAM Boot | |
0x6 = Running User OTP Boot | |
0x7 = Running Wait Boot | |
0x8 = Waiting for CPU1 to set CPU1TOCPU2IPCFLG0 to allow CPU2 to start booting |