SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Each CPU has a non-maskable interrupt (NMI) module that detects hardware errors in the system. Each NMI module has a watchdog timer that triggers a reset if the CPU does not respond to an error within a user-specified amount of time. CPU1 NMI watchdog reset (CPU1.NMIWDRS) produces an XRS. CPU2 NMI watchdog reset (CPU2.NMIWDRS) produces a CPU2.SYSRS and triggers an NMI on CPU1.
After an NMI watchdog reset, the NMIWDRSn bit in RESC is set.