In the Transmit side the timestamp captured at the internal snapshot point is earlier (advanced in time) as compared to the time at which that packet's SFD bit is output at the port's boundary. Therefore, the captured timestamp must be compensated by the egress latency and the errors in CDC sampling. This correction value must be determined/calculated by the software and written into the MAC_Timestamp_Egress_Corr_* registers.
The correction value consists of the following three components:
- External latency in the PHY layer between the output of the core and the
boundary of the port and the network. If the PHY is compliant to the IEEE 802.3
Clause 45 MMD registers, the PHY has a register indicating the maximum and
minimum egress latency. The software can read these registers and determine the
average egress latency in the PHY. Alternatively (if the PHY does not support
these registers), the egress latency must be determined from the data sheet or
timing characteristics .
- Internal latency from the internal capture point and the output of the core.
This internal egress latency can be read from the MAC_Egress_Timestamp_Latency
register. This is a read-only register and gives the latency in
scaledNanoseconds format defined in IEEE 1588 Clause 5.3.2. The latency differs
based on the active PHY interface (RMII, so on) and the operating speed. Hence,
the software must read this register after any speed change in the MAC to
determine the current internal latency.
- CDC synchronization error. The CDC synchronization error value differs
depending on the One-step timestamping mode. When One-step timestamping is
enabled, the value = (1 * period of clk_ptp_ref_i + 4 * period of clk_tx_i).
Otherwise, Two-step timestamping mode, the value = -(2 * period of
clk_ptp_ref_i).