SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
The FSIRX can operate as an independent SPI slave module. In this usage, RXCLK is connected to SPICLK and RXD0 is connected to SPISIMO. RXD1 is unused. There is no requirement for a chip select signal to be used when connected to the FSIRX. This is because the FSIRX responds to any incoming clock edge. If there is any noise or unwanted clock transitions, a flush sequence is required to resynchronize the FSIRX module with the master.
When the FSI is an SPI receiver communicating with an SPI transmitter, the application has the ability to detect frame errors, line breaks, CRC errors, ECC checks on data, as well as abruptly terminated frames. Note that the FSI can handle all of this in hardware, but the SPI transmitter must encode the information into the data to be transmitted.
Capability | Availability | Comment |
---|---|---|
Framing checks on the data frames | Yes | Standard on FSI |
Ability to detect line breaks | Yes | Can be implemented in software on the SPI transmitter but requires the use of a timer or watchdog in the transmitting SPI device. |
CRC check | Yes | Can be implemented in software on the SPI transmitter. |
ECC on data | Yes | Can be implemented in software on the SPI transmitter. |
Detection of abruptly terminated frames | Yes | This is accomplished with the FSI setting up the frame watchdog counter. |
Double edge data rate | No | |
Recovery from glitches on signal lines between frames | Yes | Whenever glitches occur on either the clock or data lines in between transmissions, the initial flush pattern of a frame discards the effects of these glitches and causes the receiver to resynchronize when the real “start-of-frame” pattern is seen. So, the ability to reject glitches in between frames is very high. |
Skew adjustment on signal lines | Yes | The FSI receiver has the ability to add delays to the incoming signal lines. |