The µDMA controller provides the
following features:
- Arm® PrimeCell
32-channel configurable µDMA controller
- Support for memory-to-memory,
memory-to-peripheral, and peripheral-to-memory in multiple transfer modes:
- Basic mode
- Ping-pong mode
- Memory scatter-gather
mode
- Peripheral scatter-gather mode
- Auto request mode
- Highly flexible and configurable
channel operation:
- Independently configured
and operated channels
- Dedicated channels for
supported on-chip modules
- Flexible channel
assignments
- One channel each for
receive and transmit path for bidirectional modules
- Dedicated channel for
software-initiated transfers
- Per-channel configurable
priority scheme
- Optional
software-initiated requests for any channel
- Two levels of priority
- Data sizes of 8, 16, and 32
bits
- Programmable transfer size in
binary steps from 1 to 1024
- Source and destination address
increment size of byte, halfword, word, or no increment
- Maskable peripheral requests
- Supports two interrupts:
- µDMA Software interrupt: µDMA generates an interrupt
when a software channel completes all its transfers
- µDMA Error interrupt: µDMA generates an interrupt an
when error is detected on a DMA transfer
- DMA transfers triggered by a
peripheral event generate a corresponding peripheral interrupt when the DMA has
completes all transfers.