SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
A quick command is a simple, compact SMBus protocol that sends an address and one bit of data in the R/S bit of the I2C header byte to communicate a command to the slave, typically a turn off or turn on. The I2C master can send a quick command by writing the target address and R/S value into the I2CMSA register followed by a write to I2CMCS with a value of 0x27. SMBus requires the slaveto be able to accept and process commands and the master to generate the quick command transactions. The master also has the capability to stop the transaction after acknowledgment from a slave.
The I2C slave requires special handling when a quick command is sent. In the case where a master sends a quick command with the R/S (data) bit cleared, the QCMDST bit in I2CSCSR is set, and the QCMDRW bit shows the data value (which, in this case, is 0) when the STOPRIS bit is set in I2CSRIS and the STOP interrupt is asserted. In this scenario, a DATARIS interrupt bit is not set. When the master sends a quick command with the R/S (data) bit set, the DATARIS bit is set to notify the slave to write a data byte to I2CSDR in which bit 7 is set. A dummy write of 0xFF to the I2CSDR register is recommended. After the write to I2CSDR, the STOP interrupt is asserted and the QCMDST and QCMDRW bits are set in the I2CSCSR register to indicate that a quick command read occurred and the last transaction was a quick command. Therefore, when the slave must receive a quick command, it expects such a command because it must write the I2CSDR with a specific value when R/S is set.