This chapter includes an overview and information about each submodule:
The ePWM Type 4 is functionally compatible to Type 2 (a Type 3 does not exist). Type 4 has the following enhancements in addition to the Type 2 features:
- Register Address Map: Additional registers are required for new features on ePWM Type 4. The ePWM register address space has been remapped for better alignment and easy usage.
- Delayed Trip Functionality: Changes have been added to achieve deadband insertion capabilities to support, for example, delayed trip functionality needed for peak current mode control type application scenarios. This has been accomplished by allowing comparator events to go into the Action Qualifier as a trigger event (Events T1 and T2). If comparator T1 / T2 events are used to edit the PWM, changes to the PWM waveform do not take place immediately. Instead, the waveform synchronizes to the next TBCLK.
- Dead-Band Generator Submodule Enhancements: Shadowing of the DBCTL register to allow dynamic configuration changes.
- One Shot and Global Load of
Registers: The ePWM Type 4 allows one shot and global load capability from shadow
to active registers to avoid partial loads in, for example, multiphase applications.
ePWM Type 4 also allows a programmable prescale of shadow to active load events. ePWM
Type 4 Global Load can simplify ePWM software by removing interrupts and making sure
that all registers are loaded at the same time.
- Trip-Zone Submodule Enhancements: Independent flags have been added to reflect the trip status for each of the TZ sources. Changes have been made to the trip-zone submodule to support certain power converter switching techniques like valley switching.
- Digital Compare Submodule Enhancements: Blanking window filter register width has been increased from 8 to 16 bits. DCCAP functionality has been enhanced to provide more programmability.
- PWM SYNC Related Enhancements: The ePWM Type 4 allows PWM SYNCOUT generation based on CMPC and CMPD events. These events can also be used for PWMSYNC pulse selection.
The ePWM Type 2 is fully compatible to Type 1. Type 2 has the following enhancements in addition to the Type 1 features:
- High-Resolution Dead-Band Capability: High-resolution capability is added to dead-band RED and FED in half-cycle clocking mode.
- Dead-Band Generator Submodule Enhancements: The ePWM Type 2 has features to enable both RED and FED on either PWM outputs. Provides increased dead band with 14-bit counters and dead-band / dead-band high-resolution registers are shadowed
- High-Resolution Extension available on ePWMxB outputs: Provides the ability to enable high-resolution period and duty cycle control on ePWMxB outputs. This is discussed in more detail in Section 26.15.
- Counter Compare Submodule Enhancements: The ePWM Type 2 allows interrupts and SOC events to be generated by additional counter compares CMPC and CMPD.
- Event Trigger Submodule
Enhancements: Prescaling logic to issue interrupt requests and ADC start of
conversion expanded up to every 15 events. This submodule allows software initialization
of event counters on SYNC event.
- Digital Compare Submodule Enhancements: Digital Compare Trip Select logic [DCTRIPSEL] has up to 12 external trip sources selected by the Input X-BAR logic in addition to an ability to OR all of them (up to 14 [external and internal sources]) to create the respective DCxEVTs.
- Simultaneous Writes to TBPRD and CMPx Registers: This feature allows writes to TBPRD, CMPA:CMPAHR, CMPB:CMPBHR, CMPC and CMPD of any ePWM module to be tied to any other ePWM module, and also allows all ePWM modules to be tied to a particular ePWM module if desired.
- Shadow to Active Load on SYNC of TBPRD and CMP Registers: This feature supports simultaneous writes of TBPRD and CMPA/B/C/D registers.
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU overhead or intervention and must be highly programmable and very flexible while being easy to understand and use. The ePWM unit described here addresses these requirements by allocating all needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources has been avoided; instead, the ePWM is built up from smaller single channel submodules with separate resources that can operate together as required to form a system. This modular approach results in an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users to understand the operation quickly.
In this document, the letter x within a signal or submodule name is used to indicate a generic ePWM instance on a device. For example, output signals EPWMxA and EPWMxB refer to the output signals from the ePWMx instance. Thus, EPWM1A and EPWM1B belong to ePWM1 and likewise EPWM4A and EPWM4B belong to ePWM4.
Type0 to Type1 Enhancements
- Increased Dead-Band Resolution: Dead-band clocking has been enhanced to allow half-cycle clocking to double resolution.
- Enhanced Interrupt and SOC Generation: Interrupts and ADC start-of-conversion can now be generated on both the TBCTR == zero and TBCTR == period events. This feature enables dual edge PWM control. Additionally, the ADC start-of-conversion can be generated from an event defined in the digital compare submodule.
- High-Resolution Period Capability: Provides the ability to enable high-resolution period. This is discussed in more detail in Section 26.15.
- Digital Compare Submodule: The digital compare submodule enhances the event triggering and trip zone submodules by providing filtering, blanking and improved trip functionality to digital compare signals. Such features are essential for peak current mode control and for support of analog comparators.
Note: The name of the sync signal that goes to the CMPSS
and GPDAC has been updated from PWMSYNC to EPWMSYNCPER (SYNCPER/PWMSYNCPER/EPWMxSYNCPER) to avoid confusion with the other EPWM sync signals EPWMSYNCI and EPWMSYNCO. For a description of these signals, see
Table 26-2.