SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
The RWDLEN1 and RWDLEN2 bit fields (see Table 34-26) determine how many bits are in each serial word in phase 1 and in phase 2, respectively, of the receive data frame.
Register | Bit | Name | Function | Type | Reset Value | |
---|---|---|---|---|---|---|
RCR1 | 7-5 | RWDLEN1 | Receive word length 1 | R/W | 000 | |
Specifies the length of every serial word in phase 1 of the receive frame. | ||||||
RWDLEN1 = 000 | 8 bits | |||||
RWDLEN1 = 001 | 12 bits | |||||
RWDLEN1 = 010 | 16 bits | |||||
RWDLEN1 = 011 | 20 bits | |||||
RWDLEN1 = 100 | 24 bits | |||||
RWDLEN1 = 101 | 32 bits | |||||
RWDLEN1 = 11X | Reserved | |||||
RCR2 | 7-5 | RWDLEN2 | Receive word length 2 | R/W | 000 | |
If a dual-phase frame is selected, RWDLEN2 specifies the length of every serial word in phase 2 of the frame. | ||||||
RWDLEN2 = 000 | 8 bits | |||||
RWDLEN2 = 001 | 12 bits | |||||
RWDLEN2 = 010 | 16 bits | |||||
RWDLEN2 = 011 | 20 bits | |||||
RWDLEN2 = 100 | 24 bits | |||||
RWDLEN2 = 101 | 32 bits | |||||
RWDLEN2 = 11X | Reserved |