SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
The ADC can be configured to generate an early interrupt pulse before the ADC conversion completes. If this option is used to start a CLA task, the CLA is able to read the result as soon as the conversion result is available in the ADC result register. This combination of just-in-time sampling along with the low interrupt response of the CLA enable faster system response and higher frequency control loops. The CLA task trigger to first instruction fetch interrupt latency is 4 cycles.
Timings for ADC conversions are shown in the timing diagrams of the ADC chapter. If the ADCCLK is a divided down version of the SYSCLK, the user has to account for the conversion time in SYSCLK cycles.
For example, if using the 12-bit ADC with ADCCLK at SYSCLK / 4, the ADC can take 10.5 ADCCLK x 4 SYSCLK = 42 SYSCLK cycles to complete a conversion. If using the ADC in 16-bit mode at the same ADCCLK, the ADC can take 29.5 ADCCLK x 4 SYSCLK = 118 SYSCLK cycles, and so on.
From a CLA perspective, the pipeline activity is shown in Table 8-5 for an N-cycle (SYSCLK) ADC conversion. The N-2 instruction arrives in the R2 phase just in time to read the result register. While the prior instructions enter the R2 phase of the pipeline too soon to read the conversion, the instructions can be efficiently used for pre-processing calculations needed by the task.
ADC Activity | CLA Activity | F1 | F2 | D1 | D2 | R1 | R2 | E | W |
---|---|---|---|---|---|---|---|---|---|
Sample | |||||||||
Sample | |||||||||
... | |||||||||
Sample | |||||||||
Conversion(Cycle 1) | Interrupt Received | ||||||||
Conversion(Cycle 2) | Task Startup | ||||||||
Conversion(Cycle 3) | Task Startup | ||||||||
Conversion(Cycle 4) | I(Cycle 4) | I(Cycle 4) | |||||||
Conversion(Cycle 5) | I(Cycle 5) | I(Cycle 5) | I(Cycle 4) | ||||||
Conversion(...) | ... | ... | ... | ... | ... | ... | ... | ||
Conversion(Cycle N-6) | I(Cycle N-6) | I(Cycle N-6) | I(Cycle N-7) | I(Cycle N-8) | I(Cycle N-9) | I(Cycle N-10) | I(Cycle N-11) | ||
Conversion(Cycle N-5) | I(Cycle N-5) | I(Cycle N-5) | I(Cycle N-6) | I(Cycle N-7) | I(Cycle N-8) | I(Cycle N-9) | I(Cycle N-10) | ||
Conversion(Cycle N-4) | I(Cycle N-4) | I(Cycle N-4) | I(Cycle N-5) | I(Cycle N-6) | I(Cycle N-7) | I(Cycle N-8) | I(Cycle N-9) | ||
Conversion(Cycle N-3) | I(Cycle N-3) | I(Cycle N-3) | I(Cycle N-4) | I(Cycle N-5) | I(Cycle N-6) | I(Cycle N-7) | I(Cycle N-8) | ||
Conversion(Cycle N-2) | Read RESULT | Read RESULT | I(Cycle N-3) | I(Cycle N-4) | I(Cycle N-5) | I(Cycle N-6) | I(Cycle N-7) | ||
Conversion(Cycle N-1) | Read RESULT | I(Cycle N-3) | I(Cycle N-4) | I(Cycle N-5) | I(Cycle N-6) | ||||
Conversion(Cycle N-0) | Read RESULT | I(Cycle N-3) | I(Cycle N-4) | I(Cycle N-5) | |||||
Conversion Complete | Read RESULT | I(Cycle N-3) | I(Cycle N-4) | ||||||
RESULT Latched | Read RESULT | I(Cycle N-3) | |||||||
RESULT Available | Read RESULT |
The ADCINTCYCLE register of the ADC can be programmed by the application to adjust the generation of the interrupt pulse to align with the ADC read operation. For example, if the first instruction in the task reads the ADC and the conversion time is N SYSCLK cycles, then the delay programmed is (N-2) - 4 = N-6.