SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
When the SPO clock polarity control bit is clear, it produces a steady state low value on the SSIClk pin. If the SPO bit is set, a steady state high value is placed on the SSIClk pin when data is not being transferred.