SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
The µDMA controller responds to two types of requests from a peripheral: single or burst. Each peripheral may support either or both types of requests. A single request means that the peripheral is ready to transfer one item, while a burst request means that the peripheral is ready to transfer multiple items.
The µDMA controller responds differently depending on whether the peripheral is making a single request or a burst request. If both are asserted, and the µDMA channel has been set up for a burst transfer, then the burst request takes precedence. Table 49-2 shows how each peripheral supports the two request types.
| Peripheral | Event That Generates Single Request | Event That Generates Burst Request |
|---|---|---|
| USB TX | None | FIFO TXRDY |
| USB RX | None | FIFO RXRDY |
| UART TX | TX FIFO not full | TX FIFO level (configurable) |
| UART RX | RX FIFO not empty | RX FIFO level (configurable) |
| SSI TX | TX FIFO not full | TX FIFO level (fixed at 4) |
| SSI RX | RX FIFO Not Empty | RX FIFO level (fixed at 4) |
| ECAT | None | |
| AES | None | Context in DMA request (AES0 Cin) Context out DMA request (AES0 Cout) Data in DMA request (AES0 Din) Data out DMA request (AES0 Dout) |
| I2C TX | TX buffer not full | TX FIFO level (configurable) |
| I2C RX | RX buffer not empty | RX FIFO level (configurable) |