SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
For a continuous export of data from the CLB peripherals, SPI RX buffers can be used. CLB data can be exported through the SPI RX buffers without CPU/CLA interventions.
For the F2838x devices, CLB1 to CLB4 have access to SPIA to SPID, respectively, as shown in Table 9-19.
CLB Instance | SPI Instance |
---|---|
CLB1 | SPIA |
CLB2 | SPIB |
CLB3 | SPIC |
CLB4 | SPID |
When the CLB to SPI data exporting is enabled, 16-bit data can be exported from CLB to SPI RX buffers. The 32-bit HLC R0 register is the data that is exported to the SPI RX buffers. The user can select which 16-bit range of the HLC R0 is exported by configuring the CLB_SPI_DATA_CTRL_HI.SHIFT. The CLB also controls when HLC R0 data must be transferred to the SPI RX buffer through CLB_SPI_DATA_CTRL_HI.STRB that selects one of the HLC event signals from the static switch block.
When CLB to SPI data exporting is required, note: