SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
During boot ROM execution, there are situations where the CPU may enter a wait loop in the code. This state can occur for a variety of reasons. Table 5-28, Table 5-29, and Table 5-30 detail the address ranges that the CPU PC register for each core will fall between if boot has entered one of these instances.
Silicon Rev0 Address Range | Silicon RevA Address Range | Description |
---|---|---|
0x3FB100 – 0x3FB106 | 0x3FB112 – 0x3FB117 | In Wait Boot Mode |
0x3FBEE2 – 0x3FBF09 | 0x3FBEEB – 0x3FBF12 | In SCI Boot waiting on autobaud lock |
0x3FE839 – 0x3FE92D | 0x3FE839 – 0x3FE92D | In NMI Handler |
0x3FE7F1 – 0x3FE823 | 0x3FE7F1 – 0x3FE823 | In PIE Vector Mismatch Handler |
0x3FE944 – 0x3FE970 | 0x3FE944 – 0x3FE970 | In ITRAP ISR |
0x3FB12A – 0x3FB12E | 0x3FB13C – 0x3FB142 | Failed secure Flash CMAC verification loop |
Silicon Rev0,A Address Range | Description |
---|---|
0x3FB41D – 0x3FB42B | In Wait Boot Mode waiting for boot command |
0x3FB459 – 0x3FB503 | In NMI Handler |
0x3FB504 – 0x3FB559 | In ITRAP ISR |
0x3FB173 – 0x3FB1B7 | In loop due to invalid CPU1TOCPU2IPCBOOTMODE value(s) and/or CPU1TOCPU2IPCFLG0 is not set |
Silicon Rev0,A Address Range | Description |
---|---|
0x180C – 0x1818 | In Wait Boot Mode waiting for boot command |
0x4018 – 0x41C2 | In NMI Handler |
0x41C4 – 0x41E8 | In Hard Fault Handler |
0x41EA – 0x421A | In Default Interrupt Handler |
0x1618 – 0x16C4 | In loop due to invalid CPU1TOCMIPCBOOTMODE value(s) and/or CPU1TOCMIPCFLG0 is not set |