SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
The types and effects of the different reset sources on the CM subsystem are discussed here. Reset for the CM subsystem is controlled by CPU1 and it is held in reset unless the user's application code on CPU1 releases the CM out of reset by writing '0' to the RESET bit of the CMRESCTL register. After updating the RESET bit, the user's software can read the RESETSTS bit of the CMRESCTL register to check the reset status of the CM. A Write to the CMRESCTL register is protected by KEY; therefore the user must put the correct value (0xA5A5) in the KEY field to make any updates to this register. Because of this, the user must always perform a 32-bit write to this register.
Following are the different reset sources on the CM subsystem.