SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Table 3-1 summarizes the various reset signals and their effect on the device. CM subsystem resets are described in Section 41.2.
Reset Source | CPU1 Core Reset (C28x, TMU, FPU, VCRC) | CPU1 Peripheral Reset | CPU2 Core Reset (C28x, TMU, FPU, VCRC) | CPU2 and CM Peripheral Reset | CPU2 and CM Held In Reset | JTAG / Debug Logic Reset | IOs | XRSn Output |
---|---|---|---|---|---|---|---|---|
POR | Yes | Yes | Yes | Yes | Yes | Yes | Hi-Z | Yes |
XRSn Pin | Yes | Yes | Yes | Yes | Yes | - | Hi-Z | - |
CPU1.SIMRESET.XRSn | Yes | Yes | Yes | Yes | Yes | - | Hi-Z | Yes |
CPU1.WDRS | Yes | Yes | Yes | Yes | Yes | - | Hi-Z | Yes |
CPU1.NMIWDRS | Yes | Yes | Yes | Yes | Yes | - | Hi-Z | Yes |
CPU1.SYSRS
(Debugger Reset) | Yes | Yes | Yes | Yes | Yes | - | Hi-Z | - |
CPU1.SIMRESET.CPU1RSn | Yes | Yes | Yes | Yes | Yes | - | Hi-Z | - |
CPU1.SCCRESET | Yes | Yes | Yes | Yes | Yes | - | Hi-Z | - |
CPU1.HWBISTRS | Yes | - | - | - | - | - | - | - |
CPU2.SYSRS (Debugger Reset) | - | - | Yes | Yes | - | - | - | - |
CPU2.WDRS | - | - | Yes | Yes | - | - | - | - |
CPU2.NMIWDRS | - | - | Yes | Yes | - | - | - | - |
CPU2.SCCRESET | - | - | Yes | Yes | - | - | - | - |
CPU2.HWBISTRS | - | - | Yes | - | - | - | - | - |
ECAT_RESET_OUT | Yes | Yes | Yes | Yes | Yes | - | Hi-Z | Yes |
TRSTn | - | - | - | - | - | Yes | - | - |
The resets can be divided into a few groups:
Whenever the CPU1 subsystem is reset, CPU2, CM and the peripherals owned by them also get reset and held in reset until CPU1 brings CPU2 and CM out of reset by writing to the CPU2RESCTL and CMRESCTL registers respectively. This is done by user application code on CPU1.
Many peripheral modules have individual resets accessible through the system control registers. For information about a module's reset state, refer to the appropriate chapter for that module.
After a POR the boot ROMs clear all of the system and message RAMs on both CPUs.