SPRUII0F May 2019 – June 2024 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Once the CRC-32 calculation is started, the BGCRC module continuously reads data from memory as a background process. These reads happen during the idle times (when the CPU, CLA or DMA is not accessing the memory block) and so does not impact functional access. The data read unit only reads data if there is no pending functional access. The data read unit begins operation by reading a block of data BGCRC_CTRL2.BLOCK_SIZE from address BGCRC_START_ADDR. Note that BGCRC_START_ADDR must be 0x80 word aligned. For a non-0x80 word aligned BGCRC_START_ADDR, the LSB bits are zeroed out to get a 0x80 word aligned BGCRC_START_ADDR. For instance, if the programmed BGCRC_START_ADDR = 0x1AF3, the internal 0x80 word aligned start address is 0x1A80.
When the data read unit reads a block of data, ECC and parity are checked. Any ECC or parity errors that occur during the read is indicated by setting the respective NMI and generating an interrupt if configured as so. The BGCRC module, however, does not write back the corrected memory contents on the occurrence of a correctable ECC error. Writing back the corrected values is handled by software.