SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The Peripheral Component Interconnect Express (PCIe) subsystem is built around a multi-lane dual-mode PCIe controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to 8.0 Gbps per lane for serial links on backplanes and printed wiring boards.
The device includes one instantiations of PCIe subsystem named PCIE1. Table 12-2454shows the PCIe subsystem allocation within device domains.
Module Instance | Domain | ||
WKUP | MCU | MAIN | |
PCIE1 | - | - | ✓ |
Figure 12-1258 provides PCIe subsystem overview.