SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There is a single R5FSS module integrated in the device MAIN domain - R5FSS0. Figure 6-70 shows the integration of R5FSS0.
Module Instance | Attributes | ||||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | ||
R5FSS0 | R5FSS0_CORE0 | PSC0 | PD24 | LPSC93 | CBASS0 |
R5FSS0_CORE1 | PSC0 | PD24 | LPSC94 | CBASS0 |
Clocks | |||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description | |
R5FSS0 | R5FSS0_CORE0_FCLK | MAIN_PLL14_HSDIV0_CLKOUT | MAIN_PLL14 | R5FSS0_CORE0 functional clock | |
R5FSS0_CORE0_ICLK | MAIN_PLL14_HSDIV0_CLKOUT | MAIN_PLL14 | R5FSS0_CORE0 interface clock | ||
R5FSS0_CORE1_FCLK | MAIN_PLL14_HSDIV0_CLKOUT | MAIN_PLL14 | R5FSS0_CORE1 functional clock | ||
R5FSS0_CORE1_ICLK | MAIN_PLL14_HSDIV0_CLKOUT | MAIN_PLL14 | R5FSS0_CORE1 interface clock | ||
Resets | |||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description | |
R5FSS0 | R5FSS0_CORE0_RST | MOD_G_RST | LPSC93 | R5FSS0_CORE0 main reset | |
R5FSS0_CORE0_DBG_RST | MOD_DBG_POR_RST | LPSC93 | R5FSS0_CORE0 debug reset (APB excluded) | ||
R5FSS0_CORE1_RST | MOD_G_RST | LPSC94 | R5FSS0_CORE1 main reset | ||
R5FSS0_CORE1_DBG_RST | MOD_POR_RST | LPSC94 | R5FSS0_CORE1 debug reset (APB excluded) |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
R5FSS0 | R5FSS0_CORE0 interrupts | ||||
R5FSS0_CORE0_PMU_0 | GIC500_SPI_IN_776 | COMPUTE_CLUSTER0 | R5FSS0_CORE0 performance monitor interrupt | Level | |
R5FSS0_CORE0_INTR_IN_18 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_18 | R5FSS0_CORE1 | ||||
R5FSS0_CORE0_VALFIQ_0 | R5FSS0_CORE0_INTR_IN_6 | R5FSS0_CORE0 | R5FSS0_CORE0 validation IRQ interrupt | Level | |
R5FSS0_CORE0_VALIRQ_0 | R5FSS0_CORE0_INTR_IN_7 | R5FSS0_CORE0 | R5FSS0_CORE0 validation FIQ interrupt | Level | |
R5FSS0_CORE0_CTI_0 | R5FSS0_CORE0_INTR_IN_8 | R5FSS0_CORE0 | R5FSS0_CORE0 cross trigger interrupt | Level | |
R5FSS0_CORE1_INTR_IN_8 | R5FSS0_CORE1 | ||||
R5FSS0_COREPAC_COMMRX_LEVEL_0_0 | R5FSS0_CORE0_INTR_IN_4 | R5FSS0_CORE0 | R5FSS0_CORE0 DTRRX full interrupt | Level | |
R5FSS0_COREPAC_COMMTX_LEVEL_0_0 | R5FSS0_CORE0_INTR_IN_5 | R5FSS0_CORE0 | R5FSS0_CORE0 DTRTX empty interrupt | Level | |
R5FSS0_CORE0_ECC_CORRECTED_PULSE_0 | ESM0_PLS_IN_608 | ESM0 | R5FSS0_CORE0 SEC ECC interrupt | Level | |
R5FSS0_CORE0_ECC_UNCORRECTED_PULSE_0 | ESM0_PLS_IN_609 | ESM0 | R5FSS0_CORE0 DED ECC interrupt | Level | |
R5FSS0_CORE0_EXP_INTR_0 | R5FSS0_CORE0_INTR_IN_16 | R5FSS0_CORE0 | R5FSS0_CORE0 RAT exception interrupt | Level | |
R5FSS0_CORE1_INTR_IN_16 | R5FSS0_CORE1 | ||||
ESM0_LVL_IN_392 | ESM0 | ||||
R5FSS0_COMMON0_ECC_SE_TO_ESM_0_0 | ESM0_LVL_IN_188 | ESM0 | R5FSS0_CORE0 ECC single-bit error interrupt (cache and TCM RAMs) | Level | |
R5FSS0_COMMON0_ECC_DE_TO_ESM_0_0 | ESM0_LVL_IN_189 | ESM0 | R5FSS0_CORE0 ECC double-bit error interrupt (cache and TCM RAMs) | Level | |
R5FSS0_CORE1 interrupts | |||||
R5FSS0_CORE1_PMU_0 | GIC500_SPI_IN_777 | COMPUTE_CLUSTER0 | R5FSS0_CORE1 performance monitor interrupt | Level | |
R5FSS0_CORE1_INTR_IN_19 | R5FSS0_CORE1 | ||||
R5FSS0_CORE0_INTR_IN_19 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_VALFIQ_0 | R5FSS0_CORE1_INTR_IN_6 | R5FSS0_CORE1 | R5FSS0_CORE1 validation IRQ interrupt | Level | |
R5FSS0_CORE1_VALIRQ_0 | R5FSS0_CORE1_INTR_IN_7 | R5FSS0_CORE1 | R5FSS0_CORE1 validation FIQ interrupt | Level | |
R5FSS0_CORE1_CTI_0 | R5FSS0_CORE1_INTR_IN_9 | R5FSS0_CORE1 | R5FSS0_CORE1 cross trigger interrupt | Level | |
R5FSS0_CORE0_INTR_IN_9 | R5FSS0_CORE0 | ||||
R5FSS0_COMMON0_COMMRX_LEVEL_1_0 | R5FSS0_CORE1_INTR_IN_4 | R5FSS0_CORE1 | R5FSS0_CORE1 DTRRX full interrupt | Level | |
R5FSS0_COMMON0_COMMTX_LEVEL_1_0 | R5FSS0_CORE1_INTR_IN_5 | R5FSS0_CORE1 | R5FSS0_CORE1 DTRTX empty interrupt | Level | |
R5FSS0_CORE1_ECC_CORRECTED_PULSE_0 | ESM0_PLS_IN_610 | ESM0 | R5FSS0_CORE1 SEC ECC interrupt | Level | |
R5FSS0_CORE1_ECC_UNCORRECTED_PULSE_0 | ESM0_PLS_IN_611 | ESM0 | R5FSS0_CORE1 DED ECC interrupt | Level | |
R5FSS0_CORE1_EXP_INTR_0 | R5FSS0_CORE0_INTR_IN_17 | R5FSS0_CORE0 | R5FSS0_CORE1 RAT exception interrupt | Level | |
R5FSS0_CORE0_INTR_IN_17 | R5FSS0_CORE1 | ||||
ESM0_LVL_IN_393 | ESM0 | ||||
R5FSS0_COMMON0_ECC_SE_TO_ESM_1_0 | ESM0_LVL_IN_190 | ESM0 | R5FSS0_CORE1 ECC single-bit error interrupt (cache and TCM RAMs) | Level | |
R5FSS0_COMMON0_ECC_DE_TO_ESM_1_0 | ESM0_LVL_IN_191 | ESM0 | R5FSS0_CORE1 ECC double-bit error interrupt (cache and TCM RAMs) | Level | |
R5FSS0_CCMR5 interrupts | |||||
R5FSS0_COMMON0_SELFTEST_ERR_PULSE_0 | ESM0_PLS_IN_612 | ESM0 | R5FSS0 self test failure interrupt | Pulse | |
R5FSS0_COMMON0_COMPARE_ERR_PULSE_0 | ESM0_PLS_IN_613 | ESM0 | R5FSS0 CPU bus compare failure interrupt | Pulse | |
R5FSS0_COMMON0_BUS_MONITOR_ERR_PULSE_0 | ESM0_PLS_IN_614 | ESM0 | R5FSS0 inactivity monitor failure interrupt | Pulse | |
R5FSS0_COMMON0_VIM_COMPARE_ERR_PULSE_0 | ESM0_PLS_IN_615 | ESM0 | R5FSS0 VIM bus compare failure interrupt | Pulse | |
R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0 | ESM0_PLS_IN_616 | ESM0 | R5FSS0 CCMR5 in self test or split mode interrupt | Pulse |