SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The MSMC2DDR bridge performs data error detection and correction (EDC) on write data received. The EDC is performed over 256-bit data quanta and uses a Hamming code algorithm supporting single error correction and double error detection.
If the write data has a single bit error the bridge indicates a single bit error through the ECC aggregator interrupts. The write data will be corrected and written to the SDRAM. The address, the error position, and the Route ID for the command caused error are logged in the DDRSS_V2A_1B_ERR_LOG1_REG and DDRSS_V2A_1B_ERR_LOG2_REG registers. The number of 1-bit EDC errors is kept in the DDRSS_V2A_1B_ERR_CNT_REG register.
If the write data has a double bit error the bridge indicates a double bit error through the ECC aggregator interrupts. The write will be executed on the SDRAM interface as a normal write and the data inside the SDRAM will be corrupted. The address and the route ID for the command caused the error are logged in the DDRSS_V2A_2B_ERR_LOG1_REG and DDRSS_V2A_2B_ERR_LOG2_REG registers. The bridge does not respond with a write error associated status for 2-bit EDC errors.
The bridge implements two EDC checkers that check EDC on each 256-bit quanta of a 512-bit data word, in a single clock cycle. Therefore, when ECC errors occur on multiple 256-bit quanta in the same 512-bit word, the error reported and logged is for the least significant 256-bits. If different quanta in the same 512-bit word have single and double bit errors simultaneously, both errors are reported via interrupts but the address and Route ID associated with only the double bit error are logged.
The bridge generates an EDC code for the read data and sends it along with its read response for checking by the receiving system master.