SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 8-3344 lists the memory-mapped registers for the NAVSS0_PVU_CFG_TLBIF. All register offset addresses not listed in Table 8-3344 should be considered as reserved locations and the register contents should not be modified.
KS3 DMA Virtual Address Translation TLB Config Region
Instance | Base Address |
---|---|
NAVSS0_IO_PVU0_CFG_TLBIF | 3600 0000h |
Offset | Acronym | Register Name | NAVSS0_IO_PVU0_CFG_TLBIF Physical Address | NAVSS0_DMA_PVU0_CFG_TLBIF Physical Address |
---|---|---|---|---|
0h + formula | PVU_CHAIN_j | TLB Chain Register | 3600 0000h + formula | 3604 0000h + formula |
20h + formula | PVU_ENTRY0_j_k | TLB Entry Register | 3600 0020h + formula | 3604 0020h + formula |
24h + formula | PVU_ENTRY1_j_k | TLB Entry Register | 3600 0024h + formula | 3604 0024h + formula |
28h + formula | PVU_ENTRY2_j_k | TLB Entry Register | 3600 0028h + formula | 3604 0028h + formula |
30h + formula | PVU_ENTRY4_j_k | TLB Entry Register | 3600 0030h + formula | 3604 0030h + formula |
34h + formula | PVU_ENTRY5_j_k | TLB Entry Register | 3600 0034h + formula | 3604 0034h + formula |
38h + formula | PVU_ENTRY6_j_k | TLB Entry Register | 3600 0038h + formula | 3604 0038h + formula |
PVU_CHAIN_j is shown in Figure 8-1662 and described in Table 8-3347.
Return to Summary Table.
The TLB chain points to another TLB. The j is the TLB number.
Offset = 0h + (j * 1000h); where j = 0h to 3Fh
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG_TLBIF | 3600 0000h + formula |
NAVSS0_DMA_IO_PVU0_CFG_TLBIF | 3604 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
EN | LOG_DIS | FAULT | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-X | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CHAIN | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CHAIN | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | EN | R/W | 0h | Enable for the TLB. 0 = disable TLB. 1 = enable TLB. |
30 | LOG_DIS | R/W | 0h | Disable Fault Logging for the TLB. 0 = enable fault logging. 1 = disable fault logging. |
29 | FAULT | R/W | 0h | A fault has been detected from this TLB that could not be logged. Will be set by hardware, and can be cleared by software. |
28-12 | RESERVED | R/W | X | |
11-0 | CHAIN | R/W | 0h | Chain to another TLB. 0 = no chain. >0 = chain to that TLB number. |
PVU_ENTRY0_j_k is shown in Figure 8-1663 and described in Table 8-3349.
Return to Summary Table.
The TLB Entry. The j is the TLB number, and the k is the entry number within a TLB. The address must be aligned to the page size.
Offset = 20h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh, k = 0h to 7h
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG_TLBIF | 3600 0020h + formula |
NAVSS0_DMA_IO_PVU0_CFG_TLBIF | 3604 0020h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBASE_L | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VBASE_L | R/W | 0h | Virtual Base Address bits 31 to 0. The address must be aligned to the page size. |
PVU_ENTRY1_j_k is shown in Figure 8-1664 and described in Table 8-3351.
Return to Summary Table.
The TLB Entry. The j is the TLB number, and the k is the entry number within a TLB. The address must be aligned to the page size.
Offset = 24h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh, k = 0h to 7h
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG_TLBIF | 3600 0024h + formula |
NAVSS0_DMA_IO_PVU0_CFG_TLBIF | 3604 0024h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VBASE_H | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | VBASE_H | R/W | 0h | Virtual Base Address bits 47 to 32. The address must be aligned to the page size. |
PVU_ENTRY2_j_k is shown in Figure 8-1665 and described in Table 8-3353.
Return to Summary Table.
The TLB Entry. The j is the TLB number, and the k is the entry number within a TLB.
Offset = 28h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh, k = 0h to 7h
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG_TLBIF | 3600 0028h + formula |
NAVSS0_DMA_IO_PVU0_CFG_TLBIF | 3604 0028h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
MODE | SEC_DEM | RESERVED | |||||
R/W-0h | R/W-0h | R/W-X | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PSECURE | RESERVED | PSIZE | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PPERM | PMEMTYPE | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PPREFETCH | PISABLE | POSABLE | PIALLOCPOL | POALLOCPOL | ||
R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | MODE | R/W | 0h | Entry mode. 0 = invalid. 1 = reserved - do not use. 2 = valid. 3 = reserved - do not use. |
29 | SEC_DEM | R/W | 0h | Enable Secure Transaction Demotion for the entry if the PVU is in secure mode. 0 = Secure Transactions are not affected. 1 = Secure Transactions that match the entry is demoted to non-secure out of the PVU. |
28-22 | RESERVED | R/W | X | |
21 | PSECURE | R/W | 0h | LPAE Field for Secure Page |
20 | RESERVED | R/W | X | |
19-16 | PSIZE | R/W | 0h | LPAE Field for Page Size. 0 = 4K. 1 = 16K. 2 = 64K. 3 = 2M. 4 = 32M. 5 = 512M. 6 = 1G. 7 = 16G. |
15-10 | PPERM | R/W | 0h | LPAE Field for Page Permissions. Bit 0 = enable user read access UR. Bit 1 = enable user write access UW. Bit 2 = enable user execute access UX. Bit 3 = enable supervisor read access SR. Bit 4 = enable supervisor write access SW. Bit 5 = enable supervisor execute access SX. |
9-8 | PMEMTYPE | R/W | 0h | LPAE Field for Page Memory Type. 0 = device. 1 = write back. 2 = write through. |
7 | RESERVED | R/W | X | |
6 | PPREFETCH | R/W | 0h | LPAE Field for Page Prefetch allowed |
5 | PISABLE | R/W | 0h | LPAE Field for Page Inner Shareable allowed |
4 | POSABLE | R/W | 0h | LPAE Field for Page Outer Shareable allowed |
3-2 | PIALLOCPOL | R/W | 0h | LPAE Field for Page Inner Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate. |
1-0 | POALLOCPOL | R/W | 0h | LPAE Field for Page Outer Allocation Policy. 0 = no allocate. 1 = write allocate. 2 = read allocate. 3 = read and write allocate. |
PVU_ENTRY4_j_k is shown in Figure 8-1666 and described in Table 8-3355.
Return to Summary Table.
The TLB Entry. The j is the TLB number, and the k is the entry number within a TLB. The address must be aligned to the page size.
Offset = 30h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh, k = 0h to 7h
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG_TLBIF | 3600 0030h + formula |
NAVSS0_DMA_IO_PVU0_CFG_TLBIF | 3604 0030h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PBASE_L | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PBASE_L | R/W | 0h | Physical Base Address bits 31 to 0. The address must be aligned to the page size. |
PVU_ENTRY5_j_k is shown in Figure 8-1667 and described in Table 8-3357.
Return to Summary Table.
The TLB Entry. The j is the TLB number, and the k is the entry number within a TLB. The address must be aligned to the page size.
Offset = 34h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh, k = 0h to 7h
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG_TLBIF | 3600 0034h + formula |
NAVSS0_DMA_IO_PVU0_CFG_TLBIF | 3604 0034h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PBASE_H | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | PBASE_H | R/W | 0h | Physical Base Address bits 47 to 32. The address must be aligned to the page size. |
PVU_ENTRY6_j_k is shown in Figure 8-1668 and described in Table 8-3359.
Return to Summary Table.
The TLB Entry. The j is the TLB number, and the k is the entry number within a TLB.
Offset = 38h + (j * 1000h) + (k * 20h); where j = 0h to 3Fh, k = 0h to 7h
Instance | Physical Address |
---|---|
NAVSS0_IO_PVU0_CFG_TLBIF | 3600 0038h + formula |
NAVSS0_DMA_IO_PVU0_CFG_TLBIF | 3604 0038h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REPLACE | ORDERID | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | X | |
4 | REPLACE | R/W | 0h | Indicates to replace the bus orderid value when matching this entry with the ORDERID field. This allows control over the orderid value when it must be restricted due to the topology for QoS reasons. 0 = bypass and use the orderid from the source transaction for the destination transaction. 1 = use the ORDERID field value for the destination transaction. |
3-0 | ORDERID | R/W | 0h | Defines the bus orderid value for this entry if hit. |