SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The HBMC may assert the memory interrupt based on the status of the memory transaction. Software needs to handle this interrupt using the MCU_FSS0_HPB0_MC_ISR register. The MCU_FSS0_HPB0_MC_ISR register can provide the status information to determine the cause of the interrupt.