SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Device masters access MSMC controlled resources through two memory map windows - internal and external.
Table 8-10 shows all MSMC associated memory regions including detailed breakdown of the MSMC internal memory mapped window.
Region | Start Address | End Address | Region Size |
---|---|---|---|
Internal memory mapped window | |||
MSMC Coherent Interface for A72SS0 | 0x00 6000 0000 | 0x00 60FF FFFF | 16 MB |
MSMC Coherent Interface for the NB0 Port of North Bridge in NAVSS0 | 0x00 6B00 0000 | 0x00 6BFF FFFF | 16 MB |
MSMC Coherent Interface for the NB1 Port of North Bridge in NAVSS0 | 0x00 6C00 0000 | 0x00 6CFF FFFF | 16 MB |
MSMC Configuration Registers(1) | 0x00 6E00 0000 | 0x00 6EFF FFFF | 16 MB |
MSMC SRAM | 0x00 7000 0000 | 0x00 7000 FFFF | 1 MB |
External memory mapped window | |||
2 GB External SDRAM Space | 0x00 8000 0000 | 0x00 FFFF FFFF | 2 GB |
8 GB External SDRAM Space(2) | 0x08 0000 0000 | 0x0F FFFF FFFF | 8 GB |
Other MSMC associated memory regions | |||
Compute Cluster ECC Aggregator 0 Configuration Registers | 0x4D 2000 0000 | 0x4D 2000 03FF | 1 KB |
Compute Cluster ECC Aggregator 1 Configuration Registers | 0x4D 2000 0400 | 0x4D 2000 07FF | 1 KB |
Compute Cluster ECC Aggregator 2 Configuration Registers | 0x4D 2000 0800 | 0x4D 2000 0BFF | 1 KB |
As shown in Table 8-10 software accesses the memory-mapped on-chip SRAM as part of the MSMC memory mapped space.