SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There is one ADC module integrated in the device MCU domain - MCU_ADC0. Figure 12-3 shows the integration of MCU_ADC0.
Table 12-3 through Table 12-5 summarize the integration of MCU_ADC0 in device MCU domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
MCU_ADC0 | WKUP_PSC0 | PD0 | LPSC15 | MCU_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
MCU_ADC0 | MCU_ADC0_VBUS_CLK | MCU_SYSCLK0/3 | WKUP_PLLCTRL0 | MCU_ADC0 interface clock |
MCU_ADC0_SYS_CLK | MCU_SYSCLK0/2 | WKUP_PLLCTRL0 | MCU_ADC0 system clock | |
MCU_ADC0_CLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | MCU_ADC0 clock. Output of multiplexer, see Figure 12-3, ADC Integration. Multiplexer control is provided via CTRLMMR_MCU_ADC0_CLKSEL[1-0] CLK_SEL bit field. Default state is WKUP_HFOSC0_CLKOUT. | |
MCU_PLL1_HSDIV1_CLKOUT | MCU_PLL1 | |||
MCU_PLL0_HSDIV1_CLKOUT | MCU_PLL0 | |||
MCU_EXT_REFCLK0 | I/O pin | |||
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
MCU_ADC0 | MCU_ADC0_RST | MOD_G_RST | LPSC15 | MCU_ADC0 reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MCU_ADC0 | MCU_ADC0_GEN_LEVEL_0 | GIC500_SPI_IN_892 | COMPUTE_CLUSTER0 | MCU_ADC0 interrupt request | Level |
R5FSS0_CORE0_INTR_IN_444 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_444 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_6 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_6 | MCU_R5FSS0_CORE1 | ||||
MCU_ADC0_ECC_CORRECTED_ERR_LEVEL_0 | MCU_ESM0_LVL_IN_10 | MCU_ESM0 | MCU_ADC0 ECC corrected error interrupt request | Level | |
MCU_ADC0_ECC_UNCORRECTED_ERR_LEVEL_0 | MCU_ESM0_LVL_IN_11 | MCU_ESM0 | MCU_ADC0 ECC uncorrected error interrupt request | Level | |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
MCU_ADC0 | MCU_ADC0_FIFO0 | ADC12_MCU_0_RX_0 | PDMA_ADC_MCU_0 | MCU_ADC0 receive request line | Pulse |
MCU_ADC0_FIFO1 | ADC12_MCU_0_RX_1 | PDMA_ADC_MCU_0 | MCU_ADC0 receive request line | Pulse |
ADC interrupts are further described in Section 12.1.1.4.1.4, Interrupts.
ADC DMA events are further described in Section 12.1.1.4.1.6, DMA Requests and Section 12.1.1.4.3.2, DMA.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.
For more information on the DMA controllers, see Chapter 10, Data Movement Architecture (DMA).