SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
If an Unexpected Response Interrupt is asserted (and there are no currently outstanding interrupts), then the following registers are loaded with information about the unexpected response:
The Unexpected Response Info Register (Base Address + 0x34) register keeps track of how many Unexpected Transaction Interrupts have occurred since the last one was serviced. Whenever an Unexpected Transaction Interrupt occurs, the value is incremented (until saturated). If an Unexpected Transaction Interrupt occurs and there is already one pending, then the counter is incremented by one, but the reporting information for the new transaction is lost.