SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 9-7 and Table 9-8 show the Arm GIC-500 memory regions.
Instance | Base Address |
---|---|
COMPUTE_CLUSTER0_GIC_DISTRIBUTOR | 0180 0000h |
COMPUTE_CLUSTER0_GIC_MESSAGE_BASED_SPIS | 0181 0000h |
COMPUTE_CLUSTER0_GIC_ITS | 0182 0000h |
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_CONTROL_LPI_0 | 0190 0000h |
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_SGI_PPI_0 | 0191 0000h |
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_CONTROL_LPI_1 | 0192 0000h |
COMPUTE_CLUSTER0_GIC_REDISTRIBUTOR_SGI_PPI_1 | 0193 0000h |
Instance | Base Address |
---|---|
COMPUTE_CLUSTER0_GIC_TRANSLATER(1) | 01000000h |
According to the Arm GIC-500 TRM, the GITS_TRANSLATER region is supposed to start at offset 30000h in the Arm GIC-500 address map. However, because the SoC implementation uses address-based method of accessing the GITS_TRANSLATER, it is accessed through a SoC assigned address and not through the 30000h offset defined in the Arm GIC-500 TRM.
For detailed Arm GIC-500 register map and register descriptions, refer to the Arm® CoreLink™ GIC-500 Generic Interrupt Controller Technical Reference Manual.