SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-1757 lists the memory-mapped registers for the MCU_CPSW0_CPTS. All register offset addresses not listed in Table 12-1757 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4600 0000h |
Offset | Acronym | Register Name | MCU_CPSW0_NUSS_CPTS Physical Address |
---|---|---|---|
0003D000h | CPSW_CPTS_IDVER_REG | MCU_CPSW0_NUSS CPTS Identification and Version Register | 4603 D000h |
0003D004h | CPSW_CPTS_CONTROL_REG | Time Sync Control Register | 4603 D004h |
0003D008h | CPSW_CPTS_RFTCLK_SEL_REG | Reference Clock Select Register | 4603 D008h |
0003D00Ch | CPSW_CPTS_TS_PUSH_REG | Time Stamp Event Push Register | 4603 D00Ch |
0003D010h | CPSW_CPTS_TS_LOAD_VAL_REG | Time Stamp Load Low Value (lower 32-bits) Register | 4603 D010h |
0003D014h | CPSW_CPTS_TS_LOAD_EN_REG | Time Stamp Load Enable Register | 4603 D014h |
0003D018h | CPSW_CPTS_TS_COMP_VAL_REG | Time Stamp Comparison Low Value (lower 32-bits) Register | 4603 D018h |
0003D01Ch | CPSW_CPTS_TS_COMP_LEN_REG | Time Stamp Comparison Length Register | 4603 D01Ch |
0003D020h | CPSW_CPTS_INTSTAT_RAW_REG | Interrupt Status Raw Register | 4603 D020h |
0003D024h | CPSW_CPTS_INTSTAT_MASKED_REG | Interrupt Status Masked Register | 4603 D024h |
0003D028h | CPSW_CPTS_INT_ENABLE_REG | Interrupt Enable Register Register | 4603 D028h |
0003D02Ch | CPSW_CPTS_TS_COMP_NUDGE_REG | Time Stamp Comparison Nudge Value Register | 4603 D02Ch |
0003D030h | CPSW_CPTS_EVENT_POP_REG | Event Interrupt Pop Register | 4603 D030h |
0003D034h | CPSW_CPTS_EVENT_0_REG | Lower 32-bits of the Event Value Register | 4603 D034h |
0003D038h | CPSW_CPTS_EVENT_1_REG | Lower Middle 32-bits of the Event Value Register | 4603 D038h |
0003D03Ch | CPSW_CPTS_EVENT_2_REG | Upper Middle 32-bits of the Event Value Register | 4603 D03Ch |
0003D040h | CPSW_CPTS_EVENT_3_REG | Upper 32-bits of the Event Value Register | 4603 D040h |
0003D044h | CPSW_CPTS_TS_LOAD_HIGH_VAL_REG | Time Stamp Load High Value (upper 32-bits) Register | 4603 D044h |
0003D048h | CPSW_CPTS_TS_COMP_HIGH_VAL_REG | Time Stamp Comparison High Value (upper 32-bits) Register | 4603 D048h |
0003D04Ch | CPSW_CPTS_TS_ADD_VAL_REG | Time Stamp Add Value Register | 4603 D04Ch |
0003D050h | CPSW_CPTS_TS_PPM_LOW_VAL_REG | Time Stamp PPM Load Low Value (lower 32-bits) Register | 4603 D050h |
0003D054h | CPSW_CPTS_TS_PPM_HIGH_VAL_REG | Time Stamp PPM Load High Value (upper 32-bits) Register | 4603 D054h |
0003D058h | CPSW_CPTS_TS_NUDGE_VAL_REG | Time Stamp Nudge Value Register | 4603 D058h |
0003D0E0h | CPSW_GENF0_COMP_LOW_REG_L | GENF0 time stamp Comparison Value Lower 32-bits Registers | 4603 D0E0h |
0003D0E4h | CPSW_GENF0_COMP_HIGH_REG_L | GENF0 time stamp Comparison Value Upper 32-bits Registers | 4603 D0E4h |
0003D0E8h | CPSW_GENF0_TS_GENF_CONTROL_REG | GENF0 Control Register Registers | 4603 D0E8h |
0003D0ECh | CPSW_GENF0_LENGTH_REG_L | GENF0 Length Value Registers | 4603 D0ECh |
0003D0F0h | CPSW_GENF0_PPM_LOW_REG_L | GENF0 PPM Value Lower 32-bits Registers | 4603 D0F0h |
0003D0F4h | CPSW_GENF0_PPM_HIGH_REG_L | GENF0 PPM Value Upper 32-bits Registers | 4603 D0F4h |
0003D0F8h | CPSW_GENF0_NUDGE_REG_L | GENF0 Nudge Value Registers | 4603 D0F8h |
0003D100h | CPSW_GENF1_COMP_LOW_REG | GENF1 time stamp Comparison Value Lower 32-bits Register | 4603 D100h |
0003D104h | CPSW_GENF1_COMP_HIGH_REG | GENF1 time stamp Comparison Value Upper 32-bits Register | 4603 D104h |
0003D108h | CPSW_GENF1_CONTROL_REG | GENF1 Control Register | 4603 D108h |
0003D10Ch | CPSW_GENF1_LENGTH_REG | GENF1 Length Value Register | 4603 D10Ch |
0003D110h | CPSW_GENF1_PPM_LOW_REG | GENF1 PPM Value Lower 32-bits Register | 4603 D110h |
0003D114h | CPSW_GENF1_PPM_HIGH_REG | GENF1 PPM Value Upper 32-bits Register | 4603 D114h |
0003D118h | CPSW_GENF1_NUDGE_REG | GENF1 Nudge Value Register | 4603 D118h |
0003D200h | CPSW_ESTF1_COMP_LOW_REG | ESTF1 time stamp Comparison Value Lower 32-bits Register | 4603 D200h |
0003D204h | CPSW_ESTF1_COMP_HIGH_REG | ESTF1 time stamp Comparison Value Upper 32-bits Register | 4603 D204h |
0003D208h | CPSW_ESTF1_CONTROL_REG | ESTF1 Control Register | 4603 D208h |
0003D20Ch | CPSW_ESTF1_LENGTH_REG | ESTF1 Length Value Register | 4603 D20Ch |
0003D210h | CPSW_ESTF1_PPM_LOW_REG | ESTF1 PPM Value Lower 32-bits Register | 4603 D210h |
0003D214h | CPSW_ESTF1_PPM_HIGH_REG | ESTF1 PPM Value Upper 32-bits Register | 4603 D214h |
0003D218h | CPSW_ESTF1_NUDGE_REG | ESTF1 Nudge Value Register | 4603 D218h |
CPSW_CPTS_IDVER_REG is shown in Figure 12-560 and described in Table 12-1048.
Return to Summary Table.
MCU_CPSW0_NUSS CPTS Identification and Version Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TX_IDENT | |||||||||||||||
R-4E8Ah | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL_VER | MAJOR_VER | MINOR_VER | |||||||||||||
R-0h | R-1h | R-Ah | |||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | TX_IDENT | R | 4E8Ah | TX Identification Value |
15-11 | RTL_VER | R | 0h | RTL version value |
10-8 | MAJOR_VER | R | 1h | Major Version Value |
7-0 | MINOR_VER | R | Ah | Minor Version Value |
CPSW_CPTS_CONTROL_REG is shown in Figure 12-561 and described in Table 12-1050.
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Time Sync Control Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TS_SYNC_SEL | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TX_GENF_CLR_EN | TS_RX_NO_EVENT | |||||
R/W-X | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
HW8_TS_PUSH_EN | HW7_TS_PUSH_EN | HW6_TS_PUSH_EN | HW5_TS_PUSH_EN | HW4_TS_PUSH_EN | HW3_TS_PUSH_EN | HW2_TS_PUSH_EN | HW1_TS_PUSH_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_PPM_DIR | TS_COMP_TOG | MODE | SEQUENCE_EN | TSTAMP_EN | TS_COMP_POLARITY | INT_TEST | CPTS_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | TS_SYNC_SEL | R/W | 0h | TS_SYNC output time stamp counter bit select |
27-18 | RESERVED | R/W | 0h | |
17 | TX_GENF_CLR_EN | R/W | 0h | GENF (and ESTF) Clear Enable. 0h = A CPTS_GENFn output is not cleared when the associated CPSW_GENF0_LENGTH_REG/ CPSW_GENF1_LENGTH_REG[31:0] is cleared to zero. 1h = A CPTS_GENFn output is cleared when the associated CPSW_GENF0_LENGTH_REG/ CPSW_GENF1_LENGTH_REG[31:0] is cleared to zero. |
16 | TS_RX_NO_EVENT | R/W | 0h | Timestamp Ethernet Receive produces no events. |
15 | HW8_TS_PUSH_EN | R/W | 0h | Hardware push 8 enable |
14 | HW7_TS_PUSH_EN | R/W | 0h | Hardware push 7 enable |
13 | HW6_TS_PUSH_EN | R/W | 0h | Hardware push 6 enable |
12 | HW5_TS_PUSH_EN | R/W | 0h | Hardware push 5 enable |
11 | HW4_TS_PUSH_EN | R/W | 0h | Hardware push 4 enable |
10 | HW3_TS_PUSH_EN | R/W | 0h | Hardware push 3 enable |
9 | HW2_TS_PUSH_EN | R/W | 0h | Hardware push 2 enable |
8 | HW1_TS_PUSH_EN | R/W | 0h | Hardware push 1 enable |
7 | TS_PPM_DIR | R/W | 0h | PPM Correction Direction |
6 | TS_COMP_TOG | R/W | 0h | Time stamp Compare Toggle mode |
5 | MODE | R/W | 0h | 64-Bit Mode. |
4 | SEQUENCE_EN | R/W | 0h | Sequence Enable. |
3 | TSTAMP_EN | R/W | 0h | Host Receive time stamp Enable |
2 | TS_COMP_POLARITY | R/W | 1h | TS_COMP Polarity |
1 | INT_TEST | R/W | 0h | Interrupt Test. |
0 | CPTS_EN | R/W | 0h | Time Sync Enable. |
CPSW_CPTS_RFTCLK_SEL_REG is shown in Figure 12-562 and described in Table 12-1052.
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RFTCLK Select Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RFTCLK_SEL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4-0 | RFTCLK_SEL | R/W | 0h | Reference clock select. This bit field is used to control an external multiplexer that selects one out of 8 clocks for time sync reference. 0h = Selects CPSWHSDIV_CLKOUT2 clock 1h = Selects MAINHSDIV_CLKOUT3 clock 2h = Selects MCU_CPTS0_RFT_CLK I/O pin 3h = Selects CPTS0_RFT_CLK I/O pin 4h = Selects MCU_EXT_REFCLK0 I/O pin 5h = Selects EXT_REFCLK1 I/O pin 6h = Selects PCIE0_TXI0_CLK clock 7h = Selects PCIE1_TXI0_CLK clock The RFTCLK_SEL value can be written only when the [0] CPTS_EN and [3] TSTAMP_EN bits are cleared to zero in the CPSW_CPTS_CONTROL_REG register. |
CPSW_CPTS_TS_PUSH_REG is shown in Figure 12-563 and described in Table 12-1054.
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Time Stamp Event Push Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D00Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PUSH | ||||||
W-X | W-0h | ||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | X | |
0 | TS_PUSH | W | 0h | Time stamp event push. |
CPSW_CPTS_TS_LOAD_VAL_REG is shown in Figure 12-564 and described in Table 12-1056.
Return to Summary Table.
Time Stamp Load Low Value Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_LOAD_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_LOAD_VAL | R/W | 0h | Time stamp load low value |
CPSW_CPTS_TS_LOAD_EN_REG is shown in Figure 12-565 and described in Table 12-1058.
Return to Summary Table.
Time Stamp Load Enable Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_LOAD_EN | ||||||
W-X | W-0h | ||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | X | |
0 | TS_LOAD_EN | W | 0h | Time Stamp Load Enable. |
CPSW_CPTS_TS_COMP_VAL_REG is shown in Figure 12-566 and described in Table 12-1060.
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Time Stamp Comparison Low Value (lower 32-bits) Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_COMP_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_COMP_VAL | R/W | 0h | Time Stamp Comparison Low Value. |
CPSW_CPTS_TS_COMP_LEN_REG is shown in Figure 12-567 and described in Table 12-1062.
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Time Stamp Comparison Length Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D01Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_COMP_LENGTH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_COMP_LENGTH | R/W | 0h | Time Stamp Comparison Length. |
CPSW_CPTS_INTSTAT_RAW_REG is shown in Figure 12-568 and described in Table 12-1064.
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Interrupt Status Register Raw
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PEND_RAW | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | TS_PEND_RAW | R/W | 0h | TS_PEND_RAW int read (before enable). |
CPSW_CPTS_INTSTAT_MASKED_REG is shown in Figure 12-569 and described in Table 12-1066.
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Interrupt Status Register Masked
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PEND | ||||||
R-X | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | |
0 | TS_PEND | R | 0h | TS_PEND masked interrupt read (after enable). |
CPSW_CPTS_INT_ENABLE_REG is shown in Figure 12-570 and described in Table 12-1068.
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Interrupt Enable Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PEND_EN | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | TS_PEND_EN | R/W | 0h | TS_PEND masked interrupt enable. |
CPSW_CPTS_TS_COMP_NUDGE_REG is shown in Figure 12-571 and described in Table 12-1070.
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Time Stamp Comparison Nudge Value Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D02Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUDGE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | NUDGE | R/W | 0h | Time stamp Comparison Nudge Value. |
CPSW_CPTS_EVENT_POP_REG is shown in Figure 12-572 and described in Table 12-1072.
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Event Interrupt Pop Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVENT_POP | ||||||
W-X | W-0h | ||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | X | |
0 | EVENT_POP | W | 0h | Event Pop. |
CPSW_CPTS_EVENT_0_REG is shown in Figure 12-573 and described in Table 12-1074.
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Lower 32-bits of the Event Value Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIME_STAMP | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TIME_STAMP | R | 0h | Time Stamp. |
CPSW_CPTS_EVENT_1_REG is shown in Figure 12-574 and described in Table 12-1076.
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Lower Middle 32-bits of the Event Value Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PREMPT_QUEUE | PORT_NUMBER | |||||
R-X | R-0h | R-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EVENT_TYPE | MESSAGE_TYPE | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQUENCE_ID | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQUENCE_ID | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R | X | |
29 | PREMPT_QUEUE | R | 0h | Prempt QUEUE |
28-24 | PORT_NUMBER | R | 0h | Port Number. |
23-20 | EVENT_TYPE | R | 0h | Time Sync Event Type |
19-16 | MESSAGE_TYPE | R | 0h | Message type. |
15-0 | SEQUENCE_ID | R | 0h | Sequence ID. |
CPSW_CPTS_EVENT_2_REG is shown in Figure 12-575 and described in Table 12-1078.
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Upper Middle 32-bits of the Event Value Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D03Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DOMAIN | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | X | |
7-0 | DOMAIN | R | 0h | Domain. |
CPSW_CPTS_EVENT_3_REG is shown in Figure 12-576 and described in Table 12-1080.
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Upper 32-bits of the Event Value Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIME_STAMP | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TIME_STAMP | R | 0h | Time Stamp. |
CPSW_CPTS_TS_LOAD_HIGH_VAL_REG is shown in Figure 12-577 and described in Table 12-1082.
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Time Stamp Load High Value (upper 32-bits) Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_LOAD_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_LOAD_VAL | R/W | 0h | Time Stamp Load high Value. |
CPSW_CPTS_TS_COMP_HIGH_VAL_REG is shown in Figure 12-578 and described in Table 12-1084.
Return to Summary Table.
Time Stamp Comparison High Value (upper 32-bits) Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_COMP_HIGH_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_COMP_HIGH_VAL | R/W | 0h | Time Stamp Comparison High Value. |
CPSW_CPTS_TS_ADD_VAL_REG is shown in Figure 12-579 and described in Table 12-1086.
Return to Summary Table.
TS Add Value Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D04Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADD_VAL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | X | |
2-0 | ADD_VAL | R/W | 0h | The ts_add_value[2:0] is added to 1 to comprise the time stamp increment value. |
CPSW_CPTS_TS_PPM_LOW_VAL_REG is shown in Figure 12-580 and described in Table 12-1088.
Return to Summary Table.
Time Stamp PPM Load Low Value (lower 32-bits) Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_PPM_LOW_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_PPM_LOW_VAL | R/W | 0h | Time Stamp PPM Low Value. |
CPSW_CPTS_TS_PPM_HIGH_VAL_REG is shown in Figure 12-581 and described in Table 12-1090.
Return to Summary Table.
Time Stamp PPM Load High Value (upper 32-bits) Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PPM_HIGH_VAL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | TS_PPM_HIGH_VAL | R/W | 0h | Time Stamp PPM High Value. |
CPSW_CPTS_TS_NUDGE_VAL_REG is shown in Figure 12-582 and described in Table 12-1092.
Return to Summary Table.
Time Stamp Nudge Value Register
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_NUDGE_VAL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | TS_NUDGE_VAL | R/W | 0h | Time stamp Nudge Value. The minimum value of the Time Stamp PPM is 0x400 (all 42 bits: CPSW_CPTS_TS_PPM_LOW_VAL_REG[31-0] TS_PPM_LOW_VAL and CPSW_CPTS_TS_PPM_HIGH_VAL_REG[9-0] TS_PPM_HIGH_VAL). |
CPSW_GENF0_COMP_LOW_REG_L is shown in Figure 12-583 and described in Table 12-1094.
Return to Summary Table.
Time Stamp Generate Function (GENF0) Comparison Low Value (lower 32-bits).
Offset = 0003D0E0h + (l * 20h); where l = 0 to 1
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D0E0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_LOW | R/W | 0h | Time Stamp Generate Function Comparison Low Value (lower 32-bits). |
CPSW_GENF0_COMP_HIGH_REG_L is shown in Figure 12-584 and described in Table 12-1096.
Return to Summary Table.
Time Stamp Generate Function (GENF0) Comparison high Value (upper 32-bits).
Offset = 0003D0E4h + (l * 20h); where l = 0 to 1
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D0E4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_HIGH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_HIGH | R/W | 0h | Time Stamp Generate Function Comparison High Value (upper 32-bits). |
CPSW_GENF0_TS_GENF_CONTROL_REG is shown in Figure 12-585 and described in Table 12-1098.
Return to Summary Table.
Time Stamp Generate Function (GENF0) Control Registers.
Offset = 0003D0E8h + (l * 20h); where l = 0 to 1
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D0E8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | POLARITY_INV | PPM_DIR | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | POLARITY_INV | R/W | 0h | Time Stamp Generate Function Polarity Invert |
0 | PPM_DIR | R/W | 0h | Time Stamp Generate Function PPM Direction. |
CPSW_GENF0_LENGTH_REG_L is shown in Figure 12-586 and described in Table 12-1100.
Return to Summary Table.
Time Stamp Generate Function (GENF0) Length Value.
Offset = 0003D0ECh + (l * 20h); where l = 0 to 1
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D0ECh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LENGTH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LENGTH | R/W | 0h | Time Stamp Generate Function Length Value |
CPSW_GENF0_PPM_LOW_REG_L is shown in Figure 12-587 and described in Table 12-1102.
Return to Summary Table.
Time Stamp Generate Function (GENF0) PPM Low Value (lower 32-bits).
Offset = 0003D0F0h + (l * 20h); where l = 0 to 1
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D0F0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PPM_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PPM_LOW | R/W | 0h | Time Stamp Generate Function PPM Low Value. |
CPSW_GENF0_PPM_HIGH_REG_L is shown in Figure 12-588 and described in Table 12-1104.
Return to Summary Table.
Time Stamp Generate Function (GENF0) PPM High Value (upper 32-bits).
Offset = 0003D0F4h + (l * 20h); where l = 0 to 1
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D0F4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PPM_HIGH | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | PPM_HIGH | R/W | 0h | Time Stamp Generate Function PPM High Value. |
CPSW_GENF0_NUDGE_REG_L is shown in Figure 12-589 and described in Table 12-1106.
Return to Summary Table.
Time Stamp Generate Function (GENF0) Nudge Value Registers.
Offset = 0003D0F8h + (l * 20h); where l = 0 to 1
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D0F8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUDGE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | NUDGE | R/W | 0h | Time Stamp Generate Function Nudge Value. |
CPSW_GENF1_COMP_LOW_REG is shown in Figure 12-590 and described in Table 12-1108.
Return to Summary Table.
Time Stamp Generate Function (GENF1) Comparison Low Value.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_LOW | R/W | 0h | Time Stamp Generate Function (GENF1) Comparison Low Value (lower 32-bits). |
CPSW_GENF1_COMP_HIGH_REG is shown in Figure 12-591 and described in Table 12-1110.
Return to Summary Table.
Time Stamp Generate Function (GENF1) Comparison high Value (upper 32-bits).
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_HIGH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_HIGH | R/W | 0h | Time Stamp Generate Function (GENF1) Comparison High Value (upper 32-bits). |
CPSW_GENF1_CONTROL_REG is shown in Figure 12-592 and described in Table 12-1112.
Return to Summary Table.
Time Stamp Generate Function (GENF1) Control Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | POLARITY_INV | PPM_DIR | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | POLARITY_INV | R/W | 0h | Time Stamp Generate Function (GENF1) Polarity Invert. |
0 | PPM_DIR | R/W | 0h | Time Stamp Generate Function (GENF1) PPM Direction. |
CPSW_GENF1_LENGTH_REG is shown in Figure 12-593 and described in Table 12-1114.
Return to Summary Table.
Time Stamp Generate Function (GENF1) Length Value
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D20Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LENGTH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LENGTH | R/W | 0h | Time Stamp Generate Function (GENF1) Length Value |
CPSW_GENF1_PPM_LOW_REG is shown in Figure 12-594 and described in Table 12-1116.
Return to Summary Table.
Time Stamp Generate Function (GENF1) PPM Low Value (lower 32-bits).
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D210h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PPM_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PPM_LOW | R/W | 0h | Time Stamp Generate Function (GENF1) PPM Low Value |
CPSW_GENF1_PPM_HIGH_REG is shown in Figure 12-595 and described in Table 12-1118.
Return to Summary Table.
Time Stamp Generate Function (GENF1) PPM High Value (upper 32-bits).
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D214h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PPM_HIGH | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | PPM_HIGH | R/W | 0h | Time Stamp Generate Function (GENF1) PPM High Value. |
CPSW_GENF1_NUDGE_REG is shown in Figure 12-596 and described in Table 12-1120.
Return to Summary Table.
Time Stamp Generate Function (GENF1) Nudge Value.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D218h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUDGE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | NUDGE | R/W | 0h | Time Stamp Generate Function (GENF1) Nudge Value . |
CPSW_ESTF1_COMP_LOW_REG is shown in Figure 12-597 and described in Table 12-1122.
Return to Summary Table.
Time Stamp Generate Function (ESTF1) Comparison Low Value.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_LOW | R/W | 0h | Time Stamp Generate Function (ESTF1) Comparison Low Value (lower 32-bits). |
CPSW_ESTF1_COMP_HIGH_REG is shown in Figure 12-598 and described in Table 12-1124.
Return to Summary Table.
Time Stamp Generate Function (ESTF1) Comparison high Value (upper 32-bits).
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_HIGH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_HIGH | R/W | 0h | Time Stamp Generate Function (ESTF1) Comparison High Value (upper 32-bits). |
CPSW_ESTF1_CONTROL_REG is shown in Figure 12-599 and described in Table 12-1126.
Return to Summary Table.
Time Stamp Generate Function (ESTF1) Control Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | POLARITY_INV | PPM_DIR | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | POLARITY_INV | R/W | 0h | Time Stamp Generate Function (ESTF1) Polarity Invert. |
0 | PPM_DIR | R/W | 0h | Time Stamp Generate Function (ESTF1) PPM Direction. |
CPSW_ESTF1_LENGTH_REG is shown in Figure 12-600 and described in Table 12-1128.
Return to Summary Table.
Time Stamp Generate Function (ESTF1) Length Value
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D20Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LENGTH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LENGTH | R/W | 0h | Time Stamp Generate Function (ESTF1) Length Value |
CPSW_ESTF1_PPM_LOW_REG is shown in Figure 12-601 and described in Table 12-1130.
Return to Summary Table.
Time Stamp Generate Function (ESTF1) PPM Low Value (lower 32-bits).
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D210h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PPM_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PPM_LOW | R/W | 0h | Time Stamp Generate Function (ESTF1) PPM Low Value |
CPSW_ESTF1_PPM_HIGH_REG is shown in Figure 12-602 and described in Table 12-1132.
Return to Summary Table.
Time Stamp Generate Function (ESTF1) PPM High Value (upper 32-bits).
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D214h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PPM_HIGH | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | PPM_HIGH | R/W | 0h | Time Stamp Generate Function (ESTF1) PPM High Value. |
CPSW_ESTF1_NUDGE_REG is shown in Figure 12-603 and described in Table 12-1134.
Return to Summary Table.
Time Stamp Generate Function (ESTF1) Nudge Value.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CPTS | 4603 D218h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUDGE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | NUDGE | R/W | 0h | Time Stamp Generate Function (ESTF1) Nudge Value . |